High speed interconnection network for a cluster of processors
AssigneeBurroughs Corporation
InventorMark L. C. Gerhold
Life of this patent
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Abstract
A high speed interconnect network for a relatively large number of processors from as few as five to a hundred or more where the information transfers are serial-by-byte in a time multiplexed manner so that when one or more processors is ready to transmit, there will be an information byte being transmitted every clock time. A bus arbiter controls access to a local bus in a round-robin fashion when one or more than one processor is requesting access to the local bus. The bus arbiter also serves for connection to an overall global loop of bus arbiters each of which has a local bus and a plurality of individual processors.
Claims4
A network of processing elements, said network comprising:
- a network bus to receive an information segment of signals in parallel;
- a plurality of processing elements coupled to said bus, and
- bus control means coupled to said bus and to each of said processing elements to grant each processing element, requesting access to said bus, access to said bus for one time period in a sequence of time periods, said access being granted according to a predetermined order;
- said network bus including two unidirectional busses, one for transferring information to said control unit and one for transferring information from said control unit to one or more processing elements.
Dependencies are inferred from the claim text.