Liquid crystal display with vertical non-single crystal semiconductor field effect transistors

Apparatus with FETs, comprising:

• a plurality of strip-like first semiconductor layers formed on a substrate to extend along first lines in a first direction;
• a plurality of strip-like second semiconductor layers formed on the substrate to extend along second lines in a second direction across the plurality of first semiconductor layers;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the first lines and extends in the first direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.

Apparatus with FETs, comprising:

• a plurality of strip-like first semiconductor layers formed on a substrate to extend along first lines in a first direction;
• a plurality of strip-like second semiconductor layers formed on the substrate to extend along second lines in a second direction across the plurality of first semiconductor layers;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the second lines and extends in the second direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.

Apparatus with FETs, comprising:

• a plurality of first semiconductor layers formed on a substrate at a plurality of intersections of a plurality of first lines extending in a first direction with a plurality of second lines extending in a second direction intersecting the plurality of first lines;
• a plurality of strip-like second semiconductor layers formed on the substrate so that each second semiconductor layer extends in the second direction across the plurality of first semiconductor layers arranged on each second line;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the first lines and extends in the first direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.

Apparatus with FETs, comprising:

• a plurality of first semiconductor layers formed on a substrate at a plurality of intersections of a plurality of first lines extending in a first direction with a plurality of second lines extending in a second direction intersecting the plurality of first lines;
• a plurality of strip-like second semiconductor layers formed on the substrate so that each second semiconductor layer extends in the second direction across the plurality of first semiconductor layers arranged on each second line;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the second lines and extends in the second direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.

Apparatus with an FET, comprising:

• a second conductive layer formed on a substrate;
• a first semiconductor layer formed on the second conductive layer;
• a second semiconductor layer formed on the first semiconductor layer;
• a third semiconductor layer formed on the second semiconductor layer;
• a first insulating layer extending on the side surface of the second semiconductor layer;
• and
• a first conductive layer extending on the first insulating layer in opposing relation to the side surface of the second semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layer has a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FET is constituted using the first and third semiconductor layers as either one of the drain and source and the other of them, the second semiconductor layer as channel region, the first conductive layer as a gate electrode and the first insulating layer as a gate insulating layer.

Apparatus with FETs, comprising:

• a plurality of strip-like second conductive layers formed on a substrate to extend along first lines in a first direction;
• a plurality of strip-like first semiconductor layers formed on the substrate to extend along second lines in a second direction across the plurality of second conductive layers;
• a plurality of strip-like second semiconductor layers, each formed on one of the first semiconductor layers to extend in the second direction;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the first lines and extends in the first direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.

Apparatus with FETs, comprising:

• a plurality of strip-like second conductive layers formed on a substrate to extend along first lines in a first direction;
• a plurality of strip-like first semiconductor layers formed on the substrate to extend along second lines in a second direction across the plurality of second conductive layers;
• a plurality of strip-like second semiconductor layers, each formed on one of the first semiconductor layers to extend in the second direction;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the second lines and extends in the second direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.

Apparatus with FETs, comprising:

• a plurality of second conductive layers formed on a substrate at a plurality of intersections of a plurality of first lines extending in a first direction with a plurality of second lines extending in a second direction intersecting the plurality of first lines;
• a plurality of strip-like first semiconductor layers formed on the substrate so that each first semiconductor layer extends in the second direction across the plurality of second conductive layers arranged on each second line;
• a plurality of strip-like second semiconductor layers, each formed on one of the first semiconductor layers to extend in the second direction;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the first lines and extends in the first direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.

Apparatus with FETs, comprising:

• a plurality of second conductive layers formed on a substrate at a plurality of intersections of a plurality of first lines extending in a first direction with a plurality of second lines extending in a second direction intersecting the plurality of first lines;
• a plurality of strip-like first semiconductor layers formed on the substrate so that each first semiconductor layer extends in the second direction across the plurality of second conductive layers arranged on each second line;
• a plurality of strip-like second semiconductor layers, each formed on one of the first semiconductor layers to extend in the second direction;
• a plurality of strip-like third semiconductor layers, each formed on one of the second semiconductor layers to extend in the second direction;
• a plurality of first insulating layers, each formed on the side surface of one of the second semiconductor layers to extend across at least the intersections of one of the second lines with the first lines;
• a plurality of strip-like first conductive layers formed on the substrate in such a manner that each first conductive layer corresponds to one of the second lines and extends in the second direction in opposing relation to the side surfaces of the second semiconductor layers through the first insulating layers, the first conductive layer being insulated from the third semiconductor layers and the first semiconductor layer;
• wherein the first, second and third semiconductor layers are formed of a non-single crystal semiconductor doped with a dangling bond neutralizer;
• the first and third semiconductor layers have the same conductivity type;
• and the second semiconductor layers have a higher resistivity than the first and third semiconductor layers;
• and
• wherein the FETs are each constituted at the intersection of each first line with each second line using the first semiconductor layer as either one of the source and drain, the third semiconductor layer as the other of the source and drain, the second semiconductor layer as a channel region, the first conductive layer as a gate electrode and the insulating layer as a gate insulating layer.