US 4,469,962 A · High-speed MESFET circuits using depletion mode MESFET signal transmission gates

Abstract

The present invention provides a circuit comprising (1) a logic element responsive to data of first and second negative voltage potentials, the logic element having a depletion mode MESFET data input gate, and (2) a depletion mode MESFET transmission gate operatively associated with the data input gate for enabling the selective serial transmission of data therethrough to the logic element in response to clock signals of third and fourth negative voltage potentials, the pinch-off threshold voltage of the data input gate being between approximately the first and second negative voltage potentials, the pinch-off threshold voltage of the transmission gate being between approximately the third and fourth negative voltage potentials, said third negative voltage potential being approximately equal to or more negative than said second negative voltage potential, said first negative voltage potential being more positive than said second negative voltage potential, and said fourth negative voltage potential being more negative than said third negative voltage potential.

Claims11

Dependent claims

An electronic circuit biased about a reference voltage and comprising:

(a) a logic element responsive to a data input signal including a high logic level of a first voltage and a low logic level of a second voltage;
(b) a clock means for supplying an oscillating electric potential clock waveform having a minimum and a maximum voltage with respect to the reference voltage, wherein:
(i) the absolute value of the clock waveform's minimum voltage is greater than the absolute value of the clock waveform's maximum voltage, and
(ii) the clock waveform's maximum voltage is approximately equal to or more negative than both the first and second voltages of the logic element;
and
(c) a metal-semiconductor field-effect transistor (MESFET) switch whose source-to-drain impedance is controlled by the voltage level of the clock waveform applied at its gate electrode and having its source connected to the input of the logic element and its drain receiving the data input signal, and wherein the switch MESFET's pinch-off voltage is more positive than the clock waveform's minimum voltage and more negative than the clock waveform's maximum voltage.

3 more elements

Dependencies are inferred from the claim text.

High-speed MESFET circuits using depletion mode MESFET signal transmission gates

Life of this patent

High-speed MESFET circuits using depletion mode MESFET signal transmission gates

Life of this patent

Abstract

Claims11