Wafer scale integrated circuit
AssigneeBurroughs Corporation
InventorHerbert Stopper
Life of this patent
Estimating the term…
Abstract
Disclosed is a substrate for an array of integrated circuit dice 10' disposed in a regular array on the monolithic wafer substrate 1. Also disposed on the wafer substrate 1 is a network 11' interconnecting various circuits 10', with other integrated circuits, disposed in the array formed on the wafer for data transfer therebetween. Terminals 12' exist in the network 11' for connection of the connections of the network with the various integrated circuits 10'. The networks are connected to a contact pad by one or more connection pads 13', for power and for data entry, and there is provided an auxiliary lead and contact pad for each network for testing each network for operability, also disclosed in the testing method.
Claims15
A wafer scale integrated circuit which incorporates integrated circuit die of different sizes;
- comprising:
- a semiconductor wafer having a major surface;
- patterned metal layers over said surface which define an array of uniformly sized cells for receiving and interconnecting said die;
- said cells having main bonding pads around their edges, auxiliary bonding pads in their interior, and conductors which connect each auxiliary bonding pad to a respective main bonding pad to form auxiliary-main bonding pad pairs;
- a plurality of said different-sized die arranged over said cells such that several large die occupy respective spaced apart areas on said surface, the spaces between said large die being smaller than the large die themselves and being at least partially filled with small die to thereby minimize any empty space between the die due to their different sizes;
- and
- selected subsets of the main and auxiliary bonding pads being aligned with the die's edges and connected to terminals on the die such that no two pads of the same pair are included in said subset.
A wafer scale integrated circuit which incorporates integrated circuit die of different sizes;
- comprising:
- a substrate having a major surface;
- patterned metal layers on said surface which define an array of uniformly sized cells for receiving and interconnecting said die;
- said cells having main bonding pads around their edges, auxiliary bonding pads in their interior, and conductors which connect each auxiliary bonding pad to a respective main bonding pad;
- and
- a plurality of die of different size, which overlie respective portions of a single cell, and which have terminals that are connected to respective subsets of that cell's main bonding pads and auxiliary bonding pads while other subsets of that single cell's bonding pads underlie and are not connected to said die.
A wafer scale integrated circuit which incorporates integrated circuit die of different sizes;
- comprising:
- a semiconductor wafer having a major surface;
- patterned metal layers over said surface which define an array of bonding pads for receiving and interconnecting said die;
- a plurality of said different-sized die arranged over said bonding pads such that several large die occupy respective spaced apart areas on said surface, the spaces between said large die being smaller than the large die themselves and being at least partially filled with small die to thereby minimize any empty space between the die due to their different sizes;
- and
- a subset of said bonding pads being aligned with the die edges and connected to terminals on the die.
Dependencies are inferred from the claim text.