Method for fabricating MOS device with self-aligned contacts

A method for fabricating an integrated circuit semiconductor device having a plurality of field effect transistor (FET) elements with self-registering electrical contacts on their source and drain regions and their gate electrodes connected to the device interconnection lines, said method comprising the steps of:

• forming a patterned layer of field oxide on a semiconductive substrate of a first conductivity type in order to form active areas free from said field oxide on the substrate surface for the formation of said FET elements;
• forming a relatively thin gate dielectric layer within said active areas;
• forming a layer of conductive material over the surface of the substrate;
• patterning said layer of conductive material into conductive gate electrodes of a predetermined shape and thickness, over said gate dielectric layer within said open areas;
• forming a first layer of dielectric material on the sides and top of each said conductive gate electrodes;
• forming, within each said active area surrounded by said field oxide, doped silicon source and drain regions of a second conductivity type material opposite to said first conductivity type of said substrate, the boundaries of said source and drain regions being determined by the edge of said field oxide and by the edges of said gate electrodes whereby said source and drain regions are self-aligned with respect to the edges of said gate electrode;
• forming a relatively thin layer of protective material over the entire device including all areas of conductive material in said active areas and said field oxide areas;
• covering said thin layer of protective material on said device with a relatively thick layer of insulating material;
• forming oversized contact openings through said insulating material over said gate electrode and over said source and drain regions where electrical contacts are to be formed;
• removing said second layer of dielectric material within said oversized contact openings;
• removing said gate oxide from the surfaces of said source and drain regions with said oversized contact openings;
• and
• depositing a metallic-type, high-electrical conductivity interconnection line pattern on the surface of the wafer extending into said contact openings thereby forming electrical connections with said source and drain regions within said contact openings.