US 4,464,728 AGranted

Charge coupled device ripple adder with nearly instantaneous carry propagation

AssigneeHughes Aircraft Company

InventorJames G. Nash

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Abstract

A ripple adder is implemented as a charge coupled device in such a manner that each carry bit propagates between succeeding full adder stages substantially simultaneously as each stage computes the sum of its two bits, so that the addition in each full adder stage may be carried out in parallel rather than in succession. The i.sup.th one of the CCD full adder stages includes charge transfer means for receiving two bits of charge, namely the i.sup.th bits of the two n-bit words which are to be summed. First and second charge storage means are provided, each having the capacity to store one bit of charge only, so that excess charge will cause an overflow. Means for sensing overflow charge stored in the second charge storage means is connected to a carry bit charge injector in the i.sup.th +1 adder stage.

Claims5

Dependent claims

A charge coupled device ripple adder having a plurality of n stages, wherein each one of said stages adds two corresponding addend bits from two n-bit words and each one of said n stages is formed on a semiconductor substrate and comprises:

input charge storing means for receiving and storing charge packets representing each of said two corresponding addend bits, said input charge storing means having a charge storing capacity equivalent to one bit of charge;
carry bit charge injecting means for injecting a carry bit charge packet into said input charge storing means, said carry bit charge injecting means comprises an electrode overlying said substrate adjacent said input charge storing means, means for injecting charge into the portion of said substrate underlying said electrode, and a transistor having a source, drain, and gate, said source and drain connected between said electrode and a voltage source;
first overflow charge storing means for receiving charge from said input charge storing means, said first overflow charge storing means comprises a charge storing diffusion in said substrate, said first overflow charge storing means having a charge storing capacity equivalent to one bit of charge;
second overflow charge storing means for receiving charge from said first overflow charge storing means, said second overflow charge storing means having a charge storing capacity equivalent to one bit of charge, and said first overflow charge storing means diffusion located between said input charge storage means and said second overflow charge storing means;
sum bit charge storing means for receiving a sum bit charge packet from either one of said input charge storing means and said second overflow charge storing means in synchronism with a clock signal .phi.W;
and
charge transfer blocking means for blocking the transfer of charge between said input charge storing means and said sum bit charge storing means, said charge transfer blocking means comprises a floating gate overlying said substrate and insulated therefrom and located between said input charge storage means and said sum bit charge storing means, said charge transfer blocking means floating gate being connected to said first overflow charge storing means charge storing diffusion to prevent charge transfer between said input charge storing means and said sum bit charge storing means whenever charge overflows into said first overflow charge storing means, said charge transfer blocking means floating gate also being connected to a carry bit charge injecting means transistor gate of a next succeeding stage so as to cause the carry bit charge injecting means of said next succeeding stage to inject a succeeding stage carry bit charge packet in response to an overflow of charge into said first overflow charge storing means, said carry bit charge injecting means transistor gate connected to a charge transfer blocking means floating gate of a next previous stage.

4 more elements

A charge coupled device ripple adder having a plurality of n stages, where each one of said stages adds two corresponding addend bits from two n-bit words and each one of said n stages is formed on a semiconductor substrate and comprises:

input charge storing means for receiving and storing charge packets representing each of said two corresponding addend bits, said input charge storing means having a charge storing capacity equivalent to one bit of charge, said input charge storing means comprises a storage electrode overlying said substrate, said storage electrode comprising a means for forming a surface potential well in an underlying portion of said substrate, said surface potential well having a charge storage capacity on the order of one bit of charge;
carry bit charge injecting means for injecting a carry bit charge packet into said input charge storing means;
first overflow charge storing means for receiving charge from said input charge storing means, said first overflow charge storing means having a charge storing capacity equivalent to one bit of charge;
second overflow charge storing means for receiving charge from said first overflow charge storing means, said second overflow charge storing means having a charge storing capacity equivalent to one bit of charge;
sum bit charge storing means for receiving a sum bit charge packet from either one of said input charge storing means and said second overflow charge storing means in synchronism with a clock signal .phi.W;
charge transfer blocking means for blocking the transfer of charge between said input charge storing means and said sum bit charge storing means wherein said charge transfer blocking means is connected to said first overflow charge storing means to prevent charge transfer between said input charge storing means and said sum bit charge storing means whenever charge overflows into said first overflow charge storing means, said charge transfer blocking means also being connected to a carry bit charge injecting means of a next succeeding stage so as to cause the carry bit charge injecting means of said next succeeding stage to inject a succeeding stage carry bit charge packet in response to an overflow of charge into said first overflow charge storing means;
and
said input charge storing means further comprising a pair of barrier electrodes, a first barrier electrode of said pair of barrier electrodes overlays said input charge storing means storage electrode and said first overflow charge storing means wherein said first barrier electrode comprises a means for forming a surface potential barrier in said substrate between said input charge storing means and said first overflow charge storing means, and a second barrier electrode of said pair of barrier electrodes overlying said storage electrode and said charge transfer blocking means, said second barrier electrode connected to receive said clock signal .phi.W.

5 more elements

input charge storing means for receiving and storing charge packets representing each of said two corresponding addend bits, said input charge storing means having a charge storing capacity equivalent to one bit of charge;
carry bit charge injecting means for injecting a carry bit charge packet into said input charge storing means;
first overflow charge storing means for receiving charge from said input charge storing means, said first overflow charge storing means having a charge storing capacity equivalent to one bit of charge;
second overflow charge storing means for receiving charge from said first overflow charge storing means, said second overflow charge storing means having a charge storing capacity equivalent to one bit of charge;
sum bit charge storing means for receiving a sum bit charge packet from either one of said input charge storing means and said second overflow charge storing means in synchronism with a clock signal .phi.W;
and
charge transfer blocking means for blocking the transfer of charge between said input charge storing means and said sum bit charge storing means wherein said charge transfer blocking means is connected to said first overflow charge storing means to prevent charge transfer between said input charge storing means and said sum bit charge storing means whenever charge overflows into said first overflow charge storing means, said charge transfer blocking means also being connected to a carry bit charge injecting means of a next succeeding stage so as to cause the carry bit charge injecting means of said next succeeding stage to inject a succeeding stage carry bit charge packet in response to an overflow of charge into said first overflow charge storing means;
and
resetting means for resetting the amount of charge storage in said input charge storing means and in said first overflow charge storing means in synchronism with a clock signal .phi.RST, said resetting means comprising an output diffusion and a first reset gate adjacent said input charge storing means, said reset gate partially overlying said output diffusion and said input charge storing means and being connected to receive said clock signal .phi.RST.

6 more elements

input charge storing for receiving and storing charge packets representing each of said two corresponding addend bits, said input charge storing means having a charge storing capacity equivalent to one bit of charge;
carry bit charge injecting means for injecting a carry bit charge packet into said input charge storing means;
first overflow charge storing means for receiving charge from said input charge storing means, said first overflow charge storing means having a charge storing capacity equivalent to one bit of charge;
second overflow charge storing means for receiving charge from said first overflow charge storing means, said second overflow charge storing means having a charge storing capacity equivalent to one bit of charge;
sum bit charge storing means for receiving a sum bit charge packet from either one of said input charge storing means and said second overflow charge storing means in synchronism with a clock signal .phi.W;
charge transfer blocking means for blocking the transfer of charge between said input charge storing means and said sum bit charge storing means wherein said charge transfer blocking means is connected to said first overflow charge storing means to prevent charge transfer between said input charge storing means and said sum bit charge storing means whenever charge overflows into said first overflow charge storing means, said charge transfer blocking means also being connected to a carry bit charge injecting means of a next succeeding stage so as to cause the carry bit charge injecting means of said next succeeding stage to inject a succeeding stage carry bit in response to an overflow of charge into said first overflow charge storing means;
and
resetting means for resetting the amount of charge storage in said input charge storing means and in said first overflow charge storing means in synchronism with a clock signal .phi.RST, said resetting means comprising a field effect transistor having a source connected to said first overflow charge storing means, a reset gate connected to receive said clock signal .phi.RST and a drain connected to a drain voltage source.

5 more elements

Dependencies are inferred from the claim text.