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US 4,463,273 AGranted
Electronic circuits and structures employing enhancement and depletion type IGFETs
AssigneeRCA Corporation
InventorAndrew G. F. Dingwall
Life of this patent
Estimating the term…
Abstract
A controllable impedance means is connected in series with the conduction path of transistors forming a complementary inverter for selectively "skewing" the inverter in a direction to center its toggle point with respect to the signals applied to the inverter input. The "skewed" inverter is thereby compensated for offsets or asymmetry in its input signals. Also disclosed is the use of skewed inverters to form memory cells which can be easily written to both binary conditions. Also disclosed is the use of the controllable impedances as "cross-unders" to enable the fabrication of very compact "skewable" inverters and memory cells.
Claims22
The combination comprising:
- a first insulated-gate field-effect transistor (IGFET) of first conductivity type and of the enhancement type;
- second and third IGFETs of second conductivity type and of the enhancement type;
- a fourth IGFET of first conductivity type and of the depletion type;
- eah IGFET having a conduction path and a control electrode for controlling the conductivity of said conduction path;
- an input line, and an output node;
- first and second power terminals for the application therebetween of an operating potential;
- means connecting the conduction path of said second IGFET between said input line and the control electrodes of said first and third IGFETs;
- means connecting one end of the conduction path of said third IGFET to the first power terminal;
- means connecting the other end of the conduction path of said third IGFET to one end of the conduction path of said first IGFET at said output node;
- means connecting the conduction path of said fourth IGFET between the other end of the conduction path of said first IGFET and said second power terminal;
- and
- means for controlling the conductivity of said second and fourth IGFETs including means for applying a signal to the gate electrodes of said second and fourth IGFETS for selectively turning-on said second IGFET and for concurrently applying a signal to the gate electrode of said fourth IGFET having a polarity and magnitude to substantially, but not wholly, decrease conduction through said fourth IGFET, when said second IGFET is turned-on.
9 more elements
An inverter comprising:
- first and second power terminals;
- an input terminal and an output terminal;
- first and second enhancement transistors of complementary conductivity type, each transistor having a control electrode and source and drain electrodes defining the ends of a conduction path;
- means connecting the control electrodes of said first and second transistor to said input terminal;
- means connecting the drain of said first and second transistors to said output terminal;
- means connecting the source of said first transistor to said first power terminal;
- and
- a controllable impedance means connected between the source electrode of said second transistor and said second power terminal for selectively shifting the transfer characteristic and the toggle point of the inverter, said controllable impedance means comprising a depletion type transistor having a control electrode and a conduction path, the conduction path of said depletion transistors being connected between the source of said second transistor and said second power terminal;
- and
- means connected to the control electrode of said depletion transistor for varying the potential applied thereto for varying the impedance of its conduction path.
7 more elements
In combination with a flip-flop comprised of two cross coupled inverters each inverter including a transistor having a main conduction path and a control electrode, the main conduction path of each transistor being connected at one end to the control electrode of the transistor of the other inverter, said one end of the main conduction path of each transistor being coupled via respective load means to a first point of operating potential;
- and one of said one end of a main conduction path defining an input point and a single gating transistor having its conduction path connected between said input point and a single input line, and wherein for one value of input data on said line said gating transistor conducts in the follower mode whereby the value of the data signal coupled to said input point is offset, the improvement comprising:
- a controllable impedance connected in series with the main conduction path of one of said inverter transistors, said controllable impedance being connected between the other end of the main conduction path of said one of said inverter transistors and a second point of operating potential, for selectively skewing said one of said two inverters in a direction to compensate for the offset of said gating transistor.
An integrated circuit structure comprising:
- a substrate;
- a first enhancement insulated-gate field-effect transistor (IGFET) of first conductivity type having source and drain regions of said first conductivity type defining the ends of a conduction channel region of second conductivity type formed on said substrate;
- second and third enhancement IGFETs, each IGFET having source and drain regions of second conductivity type defining the ends of a conduction channel of first conductivity type formed on said substrate;
- a depletion IGFET of said first conductivity type formed on said substrate having a source and drain regions defining the ends of a conduction channel region;
- each one of said IGFETs having a gate oxide region overlying its channel region and a gate electrode of conductive material formed over said gate oxide region;
- means connecting the source to drain conduction path of said depletion IGFET between the source region of said first IGFET and a first power terminal;
- means connecting the source region of said second IGFET to a second power terminal;
- means for connecting one of said source and drain regions of said third IGFET to an input signal source and means connecting the other one of said source and drain regions of said third IGFET to the gate electrodes of said first and second IGFETs;
- conductive material connecting the gate electrodes of said third IGFET and said depletion IGFET;
- and
- means connecting the drains of said first and second IGFETs in circuit to output means.
8 more elements
An integrated circuit structure comprising:
- a body of semiconductor material;
- a first enhancement insulated-gate field-effect transistor (IGFET) of first conductivity type having source and drain regions of said first conductivity type defining the ends of a conduction channel region of second conductivity type formed in said semiconductor body;
- second and third enhancement IGFETs, each IGFET having source and drain regions of second conductivity type defining the ends of a conduction channel of first conductivity type formed in said semiconductor body;
- a depletion IGFET of said first conductivity type formed in said semiconductor body having a source drain conduction path through a channel region;
- each one of said IGFETs having a gate oxide overlying its channel region and a gate electrode of conductive material formed over said channel region;
- means connecting the source to drain conduction path of said depletion IGFET between the source region of said first IGFET and a first power terminal;
- means connecting the source region of said second IGFET to a second power terminal;
- means for connecting one of said source and drain regions of said third IGFET to an input signal source and means conecting the other one of said source and drain regions of said third IGFET to the gate electrodes of said first and second IGFETs;
- means connecting the gate electrode of said third IGFET to the gate electrode of said depletion IGFET;
- and
- means connecting the drains of said first and second IGFETs in circuit to output means.
8 more elements
An integrated circuit structure comprising:
- a first enhancement insulated-gate field-effect transistor (IGFET) having source and drain regions of first conductivity type defining the ends of a conduction channel region of second conductivity type;
- second and third enhancement IGFETs, each IGFET having source and drain regions of second conductivity type defining the ends of a conduction channel of first conductivity type;
- a depletion IGFET of said first conductivity type having a source-to-drain conduction path through a channel region;
- each one of said IGFETs having a gate oxide overlying its channel region and a gate electrode of conductive material formed over said gate oxide region;
- means connecting the source to drain conduction path of said depletion IGFET between the source region of said first IGFET and a first power terminal;
- means connecting the source region of said second IGFET to a second power terminal;
- means for connecting one of said source and drain regions of said third IGFET to an input signal source and means connecting the other one of said source and drain regions of said third IGFET to the gate electrodes of said first and second IGFETs;
- conductive material connecting the gate electrodes of said third IGFET and said depletion IGFET;
- and
- means connecting the drains of said first and second IGFETs in circuit to output means.
7 more elements
Dependencies are inferred from the claim text.