US 4,461,002 A · Digital signal receiver

Abstract

A digital signal receiver is structured to receive and demodulate a digital signal. Such digital signal may comprise, for example, a television signal of character multiplex transmission having a digital signal included in the vertical blanking period of the television signal and a digital signal receiver may be structured to reproduce the digital signal from the television signal. The digital signal includes a clock run-in signal (CRI), a framing code signal (FRC) and a bit serial data signal (DA) disposed in succession. An error of the framing code or the data signal caused by a low frequency region group delay characteristic of a transmission path between the transmission and the demodulation is detected based on the digital signal. Upon detection of an error, a waveform distortion of the framing code signal and the data signal is corrected by means of a correcting circuit (15) such as an LC circuit, whereby an error of the data signal to be demodulated thereafter is prevented.

Claims11

Dependent claims

A digital signal receiver for receiving a digital signal being transmitted, said digital signal including a data signal of a bit serial fashion including data, and a specified code signal preceding said data signal, comprising:

demodulating means for receiving and demodulating said digital signal,
sampling clock generating means for generating a sampling clock signal for use in sampling said demodulated digital signal,
sampling means responsive to the output of said sampling clock generating means for reproducing said data signal by sampling said demodulated digital signal,
error detecting means responsive to said demodulated digital signal for detecting an error in bit phase of said demodulated digital signal caused by a group delay characteristic of a transmission path between transmission and demodulation with respect to detection of said specified code signal as demodulated, and
digital signal phase shifting means coupled between said demodulating means and said sampling means for shifting the phase of said demodulated digital signal, said shifting means responsive to the error detection output of said error detecting means for correcting said bit phase error.

2 more elements

A digital signal receiver for receiving a digital signal being transmitted, said digital signal including a data signal of a bit serial fashion including data, and specified code signal preceding said data signal, comprising:

demodulating means for receiving and demodulating said digital signal,
sampling clock generating means for generating a sampling clock signal for use in sampling said demodulated digital signal,
sampling means responsive to said sampling clock signal obtained from said sampling clock generating means for reproducing said data signal by sampling said demodulated digital signal,
error detecting means responsive to said demodulated digital signal for detecting an error in bit phase of said demodulated digital signal caused by a group delay characteristic of a transmission path between transmission and demodulation with respect to detecting of said demodulated specified code signal, wherein said error detecting means comprises non-coincidence detecting means for detecting non-coincidence of a predetermined code signal and said demodulated specified code signal, and
sampling clock phase shifting means responsive to error detection by said error detecting means for shifting the phase of said sampling clock signal so as to coincide with the phase of said demodulated data signal.

2 more elements

Dependencies are inferred from the claim text.

Digital signal receiver

Life of this patent

Digital signal receiver

Life of this patent

Abstract

Claims11