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US 4,459,555 AGranted
MOS Differential amplifier gain control circuit
AssigneeNational Semiconductor Corporation
InventorWilliam B. Jett, Jr.
Life of this patent
Estimating the term…
Abstract
A modulator circuit is disclosed in which a pair of differentially modulated direct currents are mirrored to an output. A control potential acts to vary the modulation without changing the direct current values. A CMOS version of a complete variable gain amplifier is detailed in which the common mode output is V.sub.CC /2 and is not changed with variations in the gain control potential or the input common mode potential.
Claims13
An MOS gain control circuit comprising:
- first and second current mirrors, each one having an input and an output;
- means for applying input currents to said inputs of said first and second current mirrors, said input currents including a direct current component and a signal component with said signal component appearing as differential variations in the direct current components of said input currents;
- and
- a control transistor having a pair of controlled terminals coupled between said inputs of said first and second current mirrors and a control terminal responsive to a voltage input whereby said signal components in said outputs of said first and second current mirrors can be varied as a function of said voltage input.
1 more element
A CMOS gain control circuit comprising:
- first and second supply rails connectable to a source of operating power;
- a first NMOS transistor having a source coupled to said first rail, and a gate and drain coupled together to a first current input terminal;
- a second NMOS transistor having a source coupled to said first rail, a gate coupled to said drain of said first transistor and a drain coupled to a first current output terminal;
- a third NMOS transistor having a source coupled to said first rail, and a gate and drain coupled together to a second current input terminal;
- a fourth NMOS transistor having a source coupled to said first rail, a gate coupled to said drain of said third transistor, and a drain coupled to a second current output terminal;
- a fifth NMOS transistor having its source-drain circuit coupled between said drains of said first and third transistors and a gate coupled to a control terminal;
- and
- means for providing inputs to said first and second input terminals whereby each of said input currents includes a d-c component and a signal component.
5 more elements
Dependencies are inferred from the claim text.