Semiconductor RAM that is accessible in magnetic disc storage format

#This invention relates to a semiconductor memory device for use in a processor system and, more particularly, to a semiconductor random access memory which may be accessed in accordance with the same format that the processor system normally uses when connected to a magnetic disc storage device, such as a floppy-disc store.

#In a typical processor system, such as a microcomputer system, a central processing unit (CPU) is coupled to a read only memory (ROM) in which the controlling program, or software, is stored, and also to a random access memory (RAM) in which incoming and outgoing data signals, as well as other processed signals, are stored; and the processor system also is coupled to other peripheral devices. Incoming data from some of the peripheral devices are supplied to the processor system by means of an input/output (I/O) interface. Such data, which passes through the I/O interface, may be written directly into suitably accessed storage locations of the RAM under the control of the CPU, or may be processed before being stored. Processed data that is stored in the RAM subsequently may be supplied to the I/O interface, either through or under control of the CPU, and thence from the I/O interface to the appropriate peripheral device. The reception of data from the I/O interface, the writing of data into the RAM, the reading, or fetching, of data from the RAM, and the transmission of data through the I/O interface to the peripheral devices all may be controlled by the appropriate program that is stored in the ROM.

#A typical CPU which may be used in processor systems of the aforenoted general type are microprocessors. Typically, an 8-bit microprocessor is provided with a 16-bit address bus, thus permitting the microprocessor to select 2.sup.16 separate address locations. In present-day nomenclature, a 16-bit address thus permits the microprocessor to be used with a memory device having 64K addressable locations. If each location is capable of storing a byte of information, the typical 8-bit microprocessor, such as the Zilog Model Z80, may be coupled to a memory device capable of storing 64K bytes. In view of the capability of most microprocessors, such a memory capacity tends to limit the "power", or data storage capacity of a typical 8-bit microprocessor. Because of this constraint, the processor system cannot handle a large quantity of data.

#The following detailed description, given by way of example, will best be understood in conjunction with the accompanying drawing in which the FIGURE is a block diagram of the semiconductor RAM system of the present invention, shown in connection with a typical processor system.

#Referring now to the drawing, there is illustrated a simplified architecture, or system interconnection, for a typical processor system comprised of a CPU 1, a bi-directional data buffer register 7, a ROM 5, a RAM 6 and a floppy disc controller 8. As is conventional, the system components are interconnected by a data bus 2, such as an 8-bit data bus, a control bus 3 and an address bus 4, the latter being, for example, a 16-bit address bus. Buses 2, 3 and 4 are coupled to each of CPU 1, ROM 5, RAM 6, data buffer 7 and floppy disc controller 8. In addition, although not illustrated herein, peripheral devices may be coupled to, for example, data bus 2 via an I/O interface, this interface also being coupled to the respective data, control and address buses.

#In addition to the foregoing elements, an oscillator 10 is provided for generating a system clock, this oscillator being coupled to CPU 1. Furthermore, a decoder 18 is coupled to address bus 4 and is adapted to decode the address signals which appear on the address bus to produce various enable signals, which also are referred to as "chip enable" or "chip select" signals. If each elements is constructed as one or more separate semiconductor "chips", then the particular chip enable signal which is produced by decoder 18 in response to decoded address signals supplied thereto enables a corresponding one (or more) of the chips which constitute the enabled element. ROM 5 and RAM 6 each include an enable input coupled, via respective leads, to decoder 18 to receive corresponding chip enable signals when the ROM or RAM is to be enabled.

#As is conventional, ROM 5 stores the usual program information which is used to control the operation of CPU 1 and, in addition, to control the overall operation of the illustrated processor system. As one example, CPU 1 may comprise the Zilog Model Z80 CPU, and ROM 5 and RAM 6 may be conventional semiconductor memory devices which are normally used and interconnected with the Zilog Model Z80 CPU.