US 4,455,654 A · Test apparatus for electronic assemblies employing a microprocessor

Abstract

A test system for functionally testing and troubleshooting microprocessor-based systems and assemblies is disclosed wherein the test system is connected in place of the microprocessor circuit of the unit being tested (UUT). The test system is itself a microprocessor-based system and includes a microprocessor circuit which is supplied with the UUT clock signal and is the same type of microprocessor circuit as is utilized by the UUT. The test system periodically switches this microprocessor into signal communication with the UUT for a single UUT bus cycle to perform UUT read or write operations. During remaining time periods, the test system microprocessor circuit is in signal communication with the remaining portion of the test system to analyze data obtained from the UUT bus during the previous UUT write or read operation and to establish the signals to be used in the next UUT write or read operation. Various test sequences are provided for testing the UUT bus, RAM, ROM, and write-responsive I/O registers. In addition, a mode of operation is provided wherein the test system interrogates a fully functional assembly of the type to be tested to derive a memory map and test parameters that permit the test system to perform RAM, ROM, and I/O tests without prior knowledge of the UUT operational sequence or allocation of address space. A test probe provides a visual indication that the logic level at a monitored circuit node is high, low, invalid, or is a sequence of pulses of all three logic levels. The test probe also provides for injection of logical high pulses, logical low pulses or an alternating pulse sequence of high and low pulses. Probe logic level detection and pulse injection can be asynchronous or can be selectively synchronized so that logic level detection or pulse injection occurs with each UUT write or read operation.

Claims56

Dependent claims

A test system for functionally testing a microprocessor-based assembly of the type wherein a microprocessor circuit communicates with at least one of a random access memory unit, a read-only memory unit and an input/output register via an interconnection bus, and a clock circuit coupling a periodic clock signal to said microprocessor circuit to establish a bus cycle of a predetermined length, said test system comprising:

a second microprocessor circuit substantially identical to said microprocessor circuit of said microprocessor-based assembly being tested;
interconnection means for connecting said test system to said microprocessor-based assembly being tested with said test system being connected to replace said microprocessor circuit of said assembly being tested, said interconnection means including means for coupling said clock signal to said second microprocessor circuit;
memory means, including means for storing instructions and data for programming said second microprocessor circuit, for supplying addressing and data signals;
switching means for selectively coupling said second microprocessor circuit between a first operational state wherein said second microprocessor is in signal communication with said memory means and a second operational state wherein said second microprocessor circuit is in signal communication with said interconnection means to supply signals to and receive signals from said interconnection bus of said microprocessor-based assembly being tested, said switching means including timing means responsive to said clock signal supplied by said microprocessor-based assembly for switching said second microprocessor circuit into said second operational state at a predetermined time, said second microprocessor circuit being maintained in said second operational state for a single bus cycle each time said switching means switches said second microprocessor from said first operational state to said second operational state.

1 more element

Apparatus for testing logic circuitry comprising:

a test probe, said test probe including an elctrode positionable in signal communication with a circuit node of logic circuitry being tested:
a first signal indicator for supplying a humanly perceivable signal and being responsive to an applied first control signal;
a second signal indicator for supplying a humanly perceivable signal and being responsive to an applied second control signal;
first signal detection means connected for receiving the signal supplied to said electrode and being connected for supplying said first control signal to said first signal indicator, said first signal detection means including means for supplying said first control signal for a predetermined time, T, each time said electrode supplies the signal of a first predetermined magnitude;
second signal detection means connected for receiving the signal supplied to said electrode and being connected for supplying said second control signal to said second signal indicator, said second signal detection means including means for supplying said second control signal for a predetermined time, T, each time said electrodes supplies a signal of a second predetermined magnitude;
third signal detection means connected for receiving the signal being supplied to said electrode, said third signal detection means including means for disabling said first and said second signal detection means for a period of time less than said predetermined time, T, each time said electrode supplies a signal having a magnitude between said first and second predetermined magnitudes.

3 more elements

Apparatus for determining a set of responses for a faultless processor controlled device comprising:

memory means containing a predetermined set of instructions;
interconnection means for connecting said apparatus to said processor controlled device;
and
apparatus processor means connected to said memory means and said interconnection means and alternating between (1) a first operational state wherein said apparatus processor means is in communication with said memory means and isolated from said processor controlled device to selectively receive said predetermined set of instructions from said memory means and provide said set of responses obtained from said processor controlled device to said memory means and (2) a second operational state wherein said apparatus processor means is in communication with said processor controlled device and isolated from said memory means to selectively execute said set of instructions by providing predetermined signals to said processor controlled device and receive signals from said processor controlled device as said set of responses;
and
means included in said memory means to retain said set of responses provided by said apparatus processor means as said set of responses for said faultless processor controlled device.

3 more elements

Apparatus for detecting faults in a processor controlled device comprising:

memory means containing a predetermined set of instructions and a predetermined set of responses;
interconnection means for connecting said apparatus to said processor controlled device;
and
apparatus processor means connected to said memory means and said interconnection means and alternating between (1) a first operational state wherein said apparatus processor means is in communication with said memory means and isolated from said processor controlled device to selectively receive said predetermined set of instructions from said memory means and provide to said memory means a set of responses previously developed from said processor controlled device and (2) a second operational state wherein said apparatus processor means is in communication with said processor controlled device and isolated from said memory means to selectively execute said set of instructions by providing predetermined signals to said processor controlled device and receive signals from said processor controlled device as said set of responses, said apparatus processor means including means for processing said set of responses from said processor controlled device to develop said predetermined signals;
and
means for detecting a fault when said predetermined set of responses differs from said set of responses from said processor controlled device.

3 more elements

Apparatus for determining a set of responses for a faultless microprocessor controlled device comprising:

memory means containing a predetermined set of instructions;
interconnection means for connecting said apparatus to said microprocessor controlled device;
an apparatus microprocessor pod connected to said memory means and said interconnection means operable alternately in (1) a first operational state wherein said apparatus microprocessor pod is in communication with said memory means and isolated from said microprocessor controlled device to selectively receive said predetermined set of instructions from said memory means and provide said set of responses to said memory means and (2) a second operational state wherein said apparatus microprocessor is in communication with said microprocessor controlled device and isolated from said memory means to selectively execute said set of instructions by providing predetermined signals to said microprocessor controlled device and receive signals from said microprocessor controlled device as said set of responses;
and
recording means in said memory means to retain said set of responses as said set of responses for said faultless microprocessor controlled device.

2 more elements

Apparatus for detecting faults in a microprocessor controlled device comprising:

memory means containing a predetermined set of instructions and a predetermined set of responses;
interconnection means for connecting said apparatus to said microprocessor controlled device;
and
an apparatus microprocessor pod connected to said memory means and said interconnection means, said apparatus microprocessor pod including an apparatus microprocessor alternating between (1) a first operational state in communication with said memory means, to selectively receive said predetermined set of instructions from said memory means and provide a set of responses to said memory means, and (2) a second operational state in communication with said microprocessor controlled device to selectively execute said set of instructions by providing predetermined signals to said microprocessor controlled device and receive signals therefrom as said set of responses;
and
comparison means in said memory means for comparing said predetermined set of responses and said set of responses and providing a visual fault indication when said responses differ.

3 more elements

Apparatus for determining a memory map for a faultless microprocessor controlled device having a removeable microprocessor and an internal clock providing periodic clock signals, comprising:

main memory means containing predetermined sets of instructions and selectable to provide one of said predetermined sets of instructions;
interconnection means for connecting said apparatus to said microprocessor controlled device where said microprocessor has been removed;
pod memory means operatively connected to said interconnection means and said main memory means responsive to said one of said predetermined sets of instructions therefrom to provide a predetermined test sequence and set of stimulation signals;
a pod microprocessor connected to said pod memory means and said interconnection means sequentially operable in a first operational state to receive said predetermined test sequence and said set of stimulation signals from said pod memory means, operable in a second operational state to execute said predetermined test sequence and provide said set of stimulation signals to said microprocessor controlled device, operable in said second operational state to receive response signals due to said stimulation signals from said microprocessor controlled device and provide said response signals to said pod memory means, and operable in said first operational state to provide said response signals to said main memory means;
switching means responsive to said periodic clock signals for switching said pod microprocessor between said first and second operational states:
and
main processor means connected to said main memory means responsive to said response signals to retain said response signals as a memory map for said faultless microprocessor controlled device.

4 more elements

Apparatus for detecting faults in a microprocessor controlled device having a removable microprocessor and an internal clock providing periodic clock signals, comprising:

main memory means containing predetermined sets of instructions and a predetermined faultless map;
interconnection means for connecting said apparatus to said microprocessor controlled device where said microprocessor has been removed;
pod memory means operatively connected to said main memory means responsive to one of said predetermined sets of instructions therefrom to provide a predetermined test sequence and set of stimulation signals;
a pod microprocessor connected to said pod memory means and said interconnection means sequentially operable in a first operational state operatively connected to said pod memory means to receive said predetermined test sequence and set of stimulation signals, operable in a second operational state operatively connected to said microprocessor controlled device to execute said predetermined test sequence by providing said stimulation signals to said microprocessor controlled device, operable in said second operational state to receive response signals due to said stimulation signals from said microprocessor controlled device and to provide said response signals to said pod memory means, and operable in said first operational state to provide said response signals to said main memory means;
switching means responsive to said periodic clock signals for switching said pod microprocessor between said first and second operational states;
and
main processor means connected to said main memory means responsive to said response signals to establish a device memory map for said microprocessor controlled device, said main processor means including means for comparing said predetermined faultless memory map with said device memory map to determine differences there between whereby faults may be detected.

4 more elements

Dependencies are inferred from the claim text.

Test apparatus for electronic assemblies employing a microprocessor

Life of this patent

Test apparatus for electronic assemblies employing a microprocessor

Life of this patent

Abstract

Claims56