Programmable signal processing device

A signal processing system comprising a signal processing device for calculating ##EQU13## said device comprising:

• a read-only memory which is programmed to store the sum of products ##EQU14## in 2.sup.M words, where B.sub.i have binary values of 0 or 1 and W.sub.i are weighting coefficients for a given application, the memory addresses being the 2.sup.M different sets of B.sub.i for words of M bits;
• input means comprising M.sub.m first registers, each of which provides storage for a word of N bits, input bus means having at least one input bus with parallel conductors for N bit positions coupled via input gate means to the first registers, input address means connected to control the input gate means to enter M words of data X.sub.i from the input bus means into corresponding input registers, M for a given application having a positive integer value equal to or less than M.sub.m, M.sub.m parallel-to-serial registers coupled via transfer gate means to the first registers, control means which includes means for controlling transfer of the data words from the first register via the transfer gate means to the parallel-to-serial registers;
• memory address means for said memory coupled to the parallel-to-serial registers to form addresses with one bit from each parallel-to-serial register in a given bit position;
• output means including an adder-accumulator and a shift circuit, the adder-accumulator having a first input from the output of said memory and a second input from the shift circuit, and a connection from the adder-accumulator output to the shift circuit input;
• said control means including timing means for providing successive clock cycles;
• the device being operative, after the data words are loaded into the parallel-to-serial registers and the shift circuit is cleared, during each clock cycle to use an address from the memory address means and supply the memory word at that address to the first input of the adder-accumulator and add it to the word from the shift circuit, and then in the shift circuit to shift the resulting word from the adder-accumulator one bit, so that after N clock cycles each word output from memory has been effectively multiplied by 2.sup.j and accumulated in the sum.