Central processing apparatus for fault-tolerant computing

In central processing apparatus for connection with a bus structure having first and second duplicative buses and a third bus, and for programmable processing of digital information including the transfer of digital information with computer memory apparatus and with computer peripheral apparatus by way of that bus structure, the improvement comprising

• A. first and second programmable digital data processing means, eash processing means being arranged for receiving signals, and for producing identical signals as the other one in response to identical received signals, and being arranged for applying produced signals to a different one of said first and second buses,
• B. multiplex means connected with said processing means and responding to select signals for applying signals from either of said first and second buses identically to both said processing means,
• C. control means for receiving signals from said third bus and for applying operating signals produced in response thereto to both said processing means, and
• D. comparator means arranged for comparing produced signals from said first processing means with produced signals from said second processing means, and for producing a fault-reporting signal in response to an invalid comparison.

In central processing apparatus having programmable digital data processing means, said apparatus transferring digital signals with memory apparatus and with peripheral apparatus by way of a bus structure having first and second duplicative buses and a third bus, the improvement comprising

• A. first and second means for connection to each of first and second duplicative buses for the transfer of signals between the first and second buses and said processing means,
• B. third means for connection to a third bus for the transfer of signals between the third bus and said processing means,
• C. input selection means responsive to a selection signal for effecting response by said processing means only to signals received on any one of the first and second buses connected with said first and second connection means,
• D. output means for applying output signals from said processing means identically to both of the first and second buses connected to said first and second connection means,
• E. fault detecting means for detecting a fault condition in the output signals from said processing means and for disabling the application of such output signals to any of said first and second connection means,
• F. power supply means for providing electrical power to at least said processing means, said selection means and said output means, and
• G. power-responsive means for responding to failing electrical power from said supply means for disabling said output means from applying signals to at least said first and second connection means.

In the processing of digital information in programmable central processing apparatus, including the transfer of digital information with memory apparatus and with peripheral apparatus by way of any of first and second duplicative buses, the improvement comprising the steps of

• A. applying signals from any of said first and second buses identically to first and second programmable digital data processing means,
• B. producing with each of said first and second processing means identical signals in response to said identical applied signals for application to any of said first and second buses,
• C. comparing said produced signals from said first processing means with said produced signals from said second processing means and producing a fault reporting signal in response to a selected difference between said compared signals, and
• D. disabling the application of produced signals from either of said processing means to either of said first and second buses in response to said fault reporting signal.