Bi-phase space code data signal reproducing circuit

Abstract

A bi-phase space code data signal reproducing circuit comprises a clock pulse supplying circuit for supplying a clock pulse having a period which is 1/N (N is an integer) of a bit period T of a bi-phase space code data signal to be reproduced, a shift register supplied with the clock pulse, for performing a shifting operation, a main flip-flop supplied with the data signal and an output signal obtained from an intermediate part of the shift register, for holding a sampling value of the data signal at a point which is substantially T/4 from the beginning of each data of the data signal, an exclusive-OR circuit supplied with an output signal of the main flip-flop and said data signal, and a reproduced data obtaining circuit for sampling an output signal of the exclusive-OR circuit by a sampling clock at a point which is substantially 3T/4 from the beginning of each data of the data signal obtained from the shift register, to obtain a reproduced data.

Dependencies are inferred from the claim text.