Power supply control for integrated circuit

A method for providing power to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip select signal to permit reading of data states in said memory, comprising the steps of:

• providing a primary power source and at least one backup power source;
• connecting said primary power source to power said memory when the voltage of said primary power source exceeds essentially the voltage of said backup power source;
• connecting said backup power source to power said memory when the voltage of said primary power source is less than a first preselected voltage;
• disabling said write enable signal provided to said memory when said primary power source is connected to power said memory and the voltage of said backup power source is less than a second preselected voltage;
• and
• disabling said write enable signal and said chip select signal provided to said memory when the voltage of said primary power source is less than a third preselected voltage.

A power control circuit for connecting one of a plurality of power sources to an integrated circuit, comprising;

• a first power terminal for receiving a primary power source;
• a second power terminal for receiving a first backup power source;
• a third power terminal for receiving a second backup power source;
• means for comparing the voltages of said second and said third power terminals and connecting the power terminal having the higher voltage to a power terminal of said integrated circuit when the voltage at said first power terminal is less than a first predetermined voltage;
• and
• means for connecting said first power terminal to said integrated circuit power terminal when the voltage at said first power terminal exceeds by a preset threshold the voltage at said integrated circuit power terminal;
• means for comparing the voltage at said first power terminal to a second predetermined voltage for producing a control signal;
• and
• means responsive to said control signal for disabling the input command signals to said integrated circuit when the voltage at said first power terminal is less than said second predetermined voltage.

A power control circuit for connecting one of a plurality of power sources to an integrated circuit memory which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading and writing of data states in said memory, comprising:

• a first power terminal for receiving a primary power source;
• a second power terminal for receiving a first backup power source;
• a third power terminal for receiving a second backup power source;
• means for comparing the voltages at said second and said third power terminals to select the one of the two terminals having the higher voltage and for connecting the higher voltage terminal supply to said memory when the voltage at said first power terminal is below a first preselected voltage;
• means for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds by a preset threshold the voltage of the higher voltage terminal of said second and third terminals;
• means connected to said second and said third power terminals for disabling said write enable signal provided to said memory when the voltage at said second or said third power terminal is less than a second preselected voltage and;
• means connected to said first power terminal for disabling said write enable and said chip select signals provided to said memory when the voltage at said first power terminal is less than a third preselected voltage.

A power control circuit for connecting one of a plurality of power sources to an integrated circuit which receives a write enable signal to permit writing of data states in said memory and receives a chip enable signal to permit reading of data states in said memory comprising circuit elements fabricated integrally with said memory, said power control circuit comprising:

• a first power terminal for receiving a primary power source;
• a second power terminal for receiving a first backup power source;
• a third power terminal for receiving a second backup power source;
• means for comparing the voltage at said first power terminal to the voltages at said second and said third power terminals for connecting said first power terminal to said memory when the voltage at said first power terminal exceeds the voltages at said first or second power terminals;
• means for comparing the voltages at said second and said third power terminals for selecting one of the terminals having the higher voltage and connecting the higher voltage terminal to said memory when the voltage at said first power terminal is less than that of said higher voltage terminal;
• a voltage divider network connected between said first power terminal and ground and having a reference node;
• a band gap reference circuit for comparing a reference voltage with the input thereto;
• means for periodically connecting the input of said band gap reference circuit to the junction node of said voltage divider network, said second power terminal and said third power terminal;
• means connected to said band gap reference circuit for disabling said write enable and said chip enable signals provided to said memory when the voltage at said first power terminal is less than a predetermined voltage;
• and
• means connected to said band gap reference circuit for disabling said write enable signal when the voltage at said first power terminal is greater than said reference voltage and the voltage at either said second or said third power terminals in less than a preselected voltage that indicates a defective backup power source, the disabling of said write enable signal indicating that one of said backup power sources is defective.