US 4,450,519 AGranted

Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories

AssigneeTexas Instruments Incorporated

InventorsKarl M. Guttag, Gerald E. Laws

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Abstract

A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. In addition to the main off-chip memory, a smaller on-chip memory (including both ROM and RAM) is provided which allows execution of instruction sequences to emulate complex instructions or interpretors (macro-instructions). The macro-instructions are indistinguishable from "native" instructions since all memory fetches and the like are generated exactly the same way, and long instruction sequences are interruptable. This on-chip memory does not affect the off-chip main memory map. Microprocessors are thus made more versatile and can be customized with little design effort.

Claims16

Dependent claims

A microprocessor system including a single-chip microprocessor device (1) comprising:

(a) a memory (2) containing a plurality of locations defined by a given set of addresses and containing program instructions and data, the program instructions being of a first type and a second type, said memory being external to said device,
(b) input/output means (3,7) external to said device for receiving and transmitting information,
(c) conductor means (4,5,6,8,9) external to said device and coupled to said memory, input/output means and said device,
(d) said microprocessor device including a central processing unit connected to said memory and said input/output means by said conductor means to couple addresses, program instruction, data and information between the memory, input/output means and central processing unit, said central processing unit comprising:
an arithmetic logic unit (10) for performing arithmetic and logic operations on data,
a plurality address/data registers for containing address and data,
an instruction register (IR) for receiving a predetermined sequence of said program instructions from said memory (2) for execution by the central processing unit, such sequence of program instructions being of a predetermined instruction set,
control means (15) including decoder means responsive to program instructions of said first type in said instruction register to produce a plurality of controls (11) for defining the operation of said arithmetic logic unit and said address/data registers of the central processing unit, and responsive to program instructions of said second type to generate auxiliary controls,
(e) an auxiliary storage unit (25A, 25B) containing a plurality of locations defined by a second set of addresses which partially overlaps said given set of addresses, with means (25G, 25D, 25F) initiated by said auxiliary controls from the control means and thereby responsive to a program instruction of said second type for transferring a different sequence of program instructions from such auxiliary storage unit to said instruction register, such different sequence being composed of said program instructions of said first type.

6 more elements

A microprocessor system, comprising:

(a) a single-chip microprocessor device having:
(i) an arithmetic logic unit for performing arithmetic and logic operations on data applied to inputs thereof to produce a result at an output thereof,
(ii) a plurality of registers including at least one address register containing a given number of bits to provide a first set of addresses within an address range,
(iii) an instruction register for receiving program instructions for execution by the microprocessor device, such program instructions being of a first type and a second type,
(iv) control means coupled to said instruction register and responsive to a program instruction of said first type to produce a plurality of controls for defining operation of the arithmetic logic unit and plurality of registers of the microprocessor device and responsive to a program instruction of said second type to produce an auxiliary control,
(v) terminals for the device for connection to parts of said system external to said microprocessor device for coupling addresses and data,
(vi) internal bus means for intercoupling said inputs and output of the arithmetic logic unit, said plurality of registers, said instruction registers, and said terminals,
(vi) control paths connecting said plurality of controls from said control means to said arithmetic logic unit, said plurality of registers, said instruction register, said terminals, and said internal bus means,
(viii) an auxiliary storage unit containing a plurality of storage locations accessed by a second set of addresses within said address range, said auxiliary storage unit storing program instructions of said first type,
(ix) auxiliary addressing means responsive to said auxiliary control from said control means for accessing said auxiliary storage unit using said address register only in response to initiation by a program instruction in said instruction register of said second type to thereby cause execution of program instructions of said first type from said auxiliary storage unit by loading such instructions into said instruction register,
(b) a memory containing a plurality of locations defined by addresses within said address range and containing program instructions of both first and second type and data, said memory having an address input and a data output,
(c) external bus means coupling said terminals of said microprocessor device to said address input and data output of said memory.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/210,106Filed 24 Nov 1980
Granted: 22 May 1984
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 15/7839
Comprising a single central processing unit: with memory
G06F 9/223
Microcontrol or microprogram arrangements: execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of…
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/3017
Arrangements for executing machine instructions, e.g. instruction decode: runtime instruction translation, e.g. macros