US 4,450,442 AGranted

Display processor for superimposed-picture display system

AssigneeMatsushita Electric Industrial Co., Ltd.

InventorKazuyuki Tanaka

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Abstract

A display processor for a raster-display type system comprising a display memory with the capacity of storing at least one page of video information to be displayed over the screen of a cathode-ray tube and a cathode-ray tube (CRT) control circuit which divides the frequency of the externally applied clock pulse to generate the address signal and the vertical and horizontal sync signals, the address signal being applied to the display memory while the vertical and horizontal sync signals are applied to the CRT display device. The present invention further adds a comparator which compares the external vertical synchronizing signal with the internal vertical sync signal and a sync circuit which responds to the output from the comparator to permit or inhibit the passage of the external clock pulse to the CRT control circuit. A plurality of such display processors are used and can be synchronized in operation so that a plurality of pages of video information can be displayed in mutually superimposed relationship on the same face of a cathode-ray tube, whereby versatile displays can be presented.

In a superimposed-picture display system for displaying a plurality of pictures in a mutually superimposed relationship, a plurality of display processors for generating display signals for displaying said plurality of pictures, respectively, each display processor being of the type comprising:

(a) a display file memory with a storage capacity capable of storing one of at least one display file of character information and graphic patterns, which can be displayed as one frame on the screen of a raster-display type cathode-ray tube, and
(b) a cathode-ray-tube control circuit which divides the frequency of a clock pulse which is supplied from another display processor to generate
(i) address signals which in turn are delivered to said display file memory so that each of said address signals specifies a memory location in which is stored video information to be displayed at a predetermined location on the screen of said raster-display type cathode-ray tube, and
(ii) vertical and horizontal sync signals which in turn are delivered to said raster-display type cathode-ray tube,
characterized by the provision that each said display processor further comprises:
(A) a comparator circuit for comparing the vertical sync signal generated by said cathode-ray-tube control circuit with an external vertical sync signal which is supplied from another display processor, and for producing an output in response thereto,
(B) a first memory means which stores the output from said comparator means in response to said clock pulse and which produces an output in response thereto,
(C) a second memory means which stores the output from said first memory means in response to the vertical sync signal generated by said cathode-ray-tube control circuit and which produces an output in response thereto,
(D) a two-input AND gate having one input of which is supplied with the output of said second memory means and another input of which is applied with said clock pulse, the AND gate applying an output in response thereto to said cathode-ray-tube control circuit, and
(E) means for resetting said first and second memory means in response to said external vertical sync signal.

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Abstract

Claims3