Manufacturing method of silicide gates and interconnects for integrated circuits
AssigneeNCR Corporation
InventorsThomas J. Hwang, Steven H. Rogers, Mary E. B. Coe
Life of this patent
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Abstract
A method of forming on a substrate a layer of silicon-rich metal silicide such as tungsten silicide, WSi.sub.x where x>2 by cosputtering a tungsten disilicide (WSi.sub.2) target and a doped silicon target on to the substrate which is maintained at room temperature. When the silicon-rich silicide is deposited on a doped polysilicon layer the resulting silicon-rich metal silicide/polysilicon sandwich layer has a low resistivity and is suitable for forming therefrom gates and interconnecting conductors for integrated circuit devices.
Claims16
A process of forming silicon-rich metal silicide on a substrate by co-sputtering a target of said metal silicide and a target of doped silicon.
The process as recited in claim l wherein said substrate is polycrystalline silicon.
A process of forming WSi.sub.x, where x is in the range of 2-3, on a substrate by cosputtering a target of WSi.sub.2 and a target of silicon.
A process of forming a low sheet resistance conductor for an integrated circuit on a semiconductor substrate having a layer of polysilicon, said process comprising:
- sputter depositing a silicon-rich tungsten silicide layer on the polysilicon layer by co-sputtering a target of tungsten disilicide and a target of silicon;
- and
- simultaneously etching the silicon-rich tungsten silicide and polysilicon dual layer into a conductor.
A process of forming a low sheet resistance gate electrode for an integrated circuit on a semiconductor substrate having an insulator layer thereon and a doped polysilicon layer on said insulator, said process comprising:
- forming a layer of silicon-rich tungsten silicide on the polysilicon by cosputtering a target of tungsten disilicide and a target of silicon;
- simultaneously etching said tungsten silicide and polysilicon dual layer to define source and drain regions in said substrate and a gate electrode corresponding to said source and drain regions;
- and
- simultaneously annealing said source and drain regions and said gate electrode.
A process of forming a semiconductor device on a semiconductor substrate having, in order, a silicon dioxide layer and a doped polysilicon layer, said process comprising:
- forming a layer of silicon-rich tungsten silicide on the polysilicon layer by cosputtering a target of tungsten disilicide and a target of silicon;
- simultaneously patterning said silicon-rich tungsten silicide and polysilicon layers into a gate electrode;
- forming at least an impurity region in said substrate in correspondence with the gate electrode;
- and
- simultaneously annealing said impurity region and said gate electrode.
A process of forming an integrated circuit on a p-type substrate having an active region, said process comprising:
- forming a relatively thin layer of silicon dioxide on said active region;
- forming a layer of polysilicon over said silicon dioxide;
- doping the polysilicon with n-type impurities;
- forming a layer of silicon-rich tungsten silicide on the polysilicon by cosputtering a target of tungsten disilicide and a target of n-type doped silicon;
- simultaneously patterning said silicon-rich silicide and polysilicon dual layer into a gate electrode corresponding to said active region;
- forming source and drain regions in said active region by implantation of n-type impurities such that said gate electrode is self-aligned with the source and drain regions;
- and
- simultaneously annealing said gate electrode and the source and drain regions.
Dependencies are inferred from the claim text.