Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection

In an integrated circuit structure, said integrated circuit structure including at least first, second, third and fourth interconnected integrated circuit chips, each of said interconnected integrated circuit chips including:

• a first non-clock chip input terminal;
• a second non-clock chip input terminal;
• a test clock (T) chip input terminal;
• a test mode control chip input terminal;
• a first chip output terminal;
• a second chip output terminal;
• a first chip receiver circuit means having an input and an output, said input of said first chip receiver circuit being connected to said first non-clock chip input terminal;
• a second chip receiver circuit means having an input and an output, said input of said second chip receiver circuit being connected to said second non-clock chip input terminal;
• a first multiplexer off chip driver circuit means having at least a first input, a second input, a control input and an output, said output of said first multiplexer off chip driver circuit means being connected to said first chip output terminal;
• a second multiplexer off chip driver circuit means having at least a first input, a second input, a control input and an output, said output of said second multiplexer off chip driver circuit means being connected to said second chip output terminal;
• first logic circuit means having at least an input and an output, said input of said first logic circuit means being connected to said output of said first receiver circuit means and said output of said first logic circuit means being connected to said first input of said first multiplexer off chip driver circuit means;
• second logic circuit means having at least an input and an output, said input of said second logic circuit means being connected to said output of said second receiver circuit means and said output of said second logic circuit means being connected to said first input of said second multiplexer off chip driver circuit means;
• Test Shift Register Latch (TSRL) circuit means having at least a first output, a second output, a first test data input (TI), a second test data input (TI), a first test clock input (T) and a second clock input (T), said first output of said Test Shift Register Latch (TSRL) circuit means being connected to said second input of said first multiplexer off-chip driver circuit means, said second output of said test shift register latch circuit means being connected to said second input of said second multiplexer off-chip driver circuit means, said first test data input (TI) of said test shift register latch circuit means being connected to said output of said first chip receiver circuit means, and said second test data input (TI) of said test shift register latch circuit means being connected to said output of said second chip receiver circuit means;
• first passive circuit connection means connecting said first and second test (T) clock inputs of said test shift register latch (TSRL) circuit means in common to said test clock (T) chip input terminal;
• second passive circuit connection means connecting said control input of said first multiplexer off-chip driver circuit means and said control input of said second multiplexer off-chip driver circuit means in common to said test mode control chip input terminal.

In a packaging structure for containing and interconnecting one, two, three . . . to n, integrated circuit chips, where n is a positive integer, said packaging structure comprising:

• wiring means including a plurality of accessible packaging structure contacts, said wiring means interconnecting said n integrated circuit chips and further including wiring for providing electrical signals and energy, such as input, output, power and timing signals, to the integrated circuits on said integrated circuit chips;
• each chip of said n interconnected integrated circuit chips including at least one test shift register latch (TSRL) circuit;
• each said test shift register latch (TSRL) circuit including a scan input, a scan output, a first latch circuit (L1) and a second latch circuit (L2), said first and said second latch circuits of each of said test shift register latch (TSRL) circuits being serially connected between said scan input and said scan output thereof, each said first latch circuit of each of said test shift register latch (TSRL) circuits further including an A-clock input terminal, and a test data output terminal, each of said second latch circuits of each of said test shift register latch (TSRL) circuits further including a B-clock input terminal, a test data input terminal (T), and a test clock input terminal (T);
• each one of said n interconnected integrated circuit chips having a chip scan input pad, a chip scan output pad, a chip A-clock input pad, a chip B-clock input pad and a chip test clock (T) pad,
• each one of said n interconnected integrated circuit chips including first interconnection means for serially interconnecting said scan input and scan output of each of said at least one test shift register latch circuits contained on said integrated circuit chip between said chip scan input pad and said chip scan output pad of said chip,
• each one of said n interconnected integrated circuit chips including second interconnection means for connecting in common said A-clock input terminals of said at least one test shift register latch (TSRL) circuit contained on said chip and said chip A-clock input pad contained on said chip;
• each one of said n interconnected integrated circuit chips including third interconnection means for connecting in common said B-clock input terminals of said at least one test shift register latch (TSRL) circuit contained on said chip and said chip B-clock input pad contained on said chip;
• each one of said n interconnected integrated circuit chips including fourth interconnection means for connecting in common said test clock input terminal (T) of each of said at least one test shift register latch (TSRL) circuit contained on said chip and said chip test clock (T) pad;
• said wiring means including wiring for serially interconnecting said chip scan input pads and said chip scan output pads of said n integrated circuit chips, serially in the order recited, between a package scan input contact and a package scan output contact;
• said wiring means further including an accessible package A clock input contact and wiring for interconnecting in common said package A-clock input contact and said A-clock input pad of each of said n integrated circuit chips;
• said wiring means further including an accessible package B clock input contact and wiring for interconnecting in common said package B-clock input contact and said B-clock input pad of each of said n integrated circuit chips;
• said wiring means further including an accessible package test clock input (T) contact and wiring for interconnecting in common said package test clock input (T) contact and said chip test clock input (T) pad of each of said n integrated circuit chips;
• each of said n interconnected integrated circuit chips including at least one on chip receiver circuit having an off chip input and an on chip output, and wherein said output of said at least one on chip receiver circuit is connected to said test data input TI of said at least one test shift register latch circuits contained on said same chip as said at least one on chip receiver circuit;
• each of said n interconnected integrated circuit chips including at least one off chip driver circuit, each of said at least one off chip driver circuit having a first input, a second input, an off-chip output and a control input for selecting either said first input or said second input, said first input of each said at least one off chip driver circuits being connected to test data output terminal of said at least one test shift register latch (TSRL) circuit on said same chip;
• each of said n interconnected integrated circuit chips including a logic circuit having at least one input and at least one output, said input of said logic circuit on each of said n integrated circuit chips being connected to the output of said at least one on chip receiver circuit contained on said same chip and said output of said logic circuit on each of said n integrated circuit chips being connected to the second input of said at least one off chip driver on said same chip;
• and
• each of said n interconnected integrated circuit chips including a test mode control pad connected to said control input of said at least one off chip driver on said same chip, and wherein said wiring means further includes n accessible package chip test mode control contacts and wiring for interconnecting each of said n accessible package chip test mode control contacts to a discrete one of said n test mode control pads of said n integrated circuit chips.

An improved high density packaging structure (FIG. 10) including a plurality of interconnected integrated circuit chips, said packaging structure including circuitry whereby each of said plurality of interconnected integrated circuit chips may be independently tested while remaining interconnected in said packaging structure, and said independent testing of each of said integrated circuit chips is accomplished without the use of a precision probe and a high speed step and repeat mechanism, said improved high density packaging structure comprising:

• a substrate having a first generally planar surface and a second generally planar surface, said second generally planar surface being spaced from and essentially parallel to said first generally planar surface;
• a plurality of spaced apart groups of contact pads contained on said first generally planar surface of said substrate;
• a pattern of packaging structure contacts on said second generally planar surface of said substrate;
• said packaging structure contacts including a single packaging structure scan in contact (Scan IN, FIG. 10), a single packaging structure scan out contact (Scan OUT, FIG. 10), a single packaging structure test clock contact (Test Clock T, FIG. 10), a single packaging structure A-clock contact (Clock A, FIG. 10), a single packaging structure B-clock contact (Clock B, FIG. 10), and a plurality of test mode contacts (TMC1, TMC2, TMC3, TMC4, etc., FIG. 10);
• a plurality of conductors supported by said substrate and interconnecting said contact pads of said groups of contact pads and said contacts of said pattern of packaging structure contacts;
• each chip of said plurality of integrated circuit chips having a group of chip contact pads, said group of chip contacts of each chip of said integrated circuit chips corresponding to at least one group of contact pads of said substrate;
• connection means connecting the group of chip contact pads of each chip to a predetermined one of said groups of contact pads of said substrate;
• each chip of said plurality of integrated circuit chips containing test circuitry, said test circuitry contained on each chip of said plurality of integrated circuit chips includes scan-in scan-out circuit means, where said scan-in scan-out circuit means on each chip of said plurality of integrated circuit chips includes a scan-in chip contact pad, a scan-out chip contact pad, an A-clock chip contact pad, and a B-clock chip contact pad, and wherein said scan-in scan-out circuit means on each chip of said plurality of integrated circuit chips include test shift register latch (TSRL) circuit means having at least one test shift register latch (TSRL) circuit, said at least one test shift register latch (TSRL) circuit includes a test data port having a test data input (T1) and test clock input (T) and wherein each of said plurality of interconnected integrated circuit chips includes a test clock (T) chip contact pad connected to said test clock input (T) of said at least one test shift register latch (TSRL);
• at least one receiver circuit contained on each of said plurality of interconnected integrated circuit chips, each of said receiver circuits being connected to a test shift register latch;
• at least off-chip one driver circuit contained on each of said plurality of interconnected integrated circuit chips, each of said driver circuits being connected to a test shift register latch and to a test mode contact;
• said plurality of conductors including conductors for selectively connecting said test circuitry of each chip of said plurality of integrated chips to said single packaging structure scan in contact, said single packaging structure scan out contact, said single packaging structure test clock contact, said single packaging structure A-block contact, said single packaging structure B-clock contact and said plurality of package test mode contacts.