Process for producing NPN type lateral transistor with minimal substrate operation interference

A method for forming an array of sub-micron dimensioned NPN-type lateral transistors on a substrate doped P-type, wherein each transistor is formed comprising the following steps:

• masking the substrate to outline a pair of boundary regions for each semi-array of active regions to comprise a transistor;
• slotting the substrate in said boundary regions to a given depth to form spaced apart slots removing any masking material from the substrate;
• angle evaporating etch resist to cover the active regions of the substrate between slots;
• and the edges of said slots to a depth less than said given depth by way of the slots;
• etching away the substrate below said depth less than the given depth sufficiently to separate the semi-arrays of active regions from the substrate except at spaced apart locations therealong;
• oxidizing the substrate to fill in the portions etched away and the slots;
• slotting the substrate orthogonally to the first mentioned slots to provide second slots with orthogonal pairs of slots defining active regions for the respective transistors;
• doping the regions defined by orthogonal pairs of slots P+ through a single corresponding edge of each of the second slots and driving in the P+ doping;
• doping of said last mentioned regions through both edges of each slot of said second slots N+ and driving in the N+ doping;
• oxidizing the substrate to completely isolate said active regions from the substrate;
• and,
• establishing electrical connections to the outer N+ regions and inner P+P region.