Speed measurement system with means for calculating the exact time period of a known quantity of speed pulses

For use with a digital fuel control for an engine including a high speed clock and means producing a sampling pulse, a speed measurement system comprising:

• means including engine driven means producing a square wave signal proportional to engine speed,
• a synchronizing circuit connected to receive said square wave signal and convert said signal to a series of sharp reset pulses of the same frequency as said signal,
• first and second counters connected to said synchronizing circuit and high speed clock respectively, such that the initiation of the sample pulse enables said synchronizing circit to conduct reset pulses to said first and second counters, receipt of each of said reset pulses by said second counter causing said counter to be reset to zero and begin counting high speed counts anew, and said first counter counts said reset pulses,
• first and second memory means connected to said second counter with said first memory means connected to accumulate and hold clock counts occurring between the initiation of said sampling pulse and the previous reset pulse and said second memory means connected to accumulate and hold clock counts occurring between the termination of said sampling pulse and the previous reset pulse,
• first subtractor circuit means connected to said first and second memory means producing an output representing the difference in counts contained in said first and second memory means,
• a divider circuit connected to said first counter and means responsive to the termination of said sampling pulse to transfer the counts of said first counter to said divider circuit,
• third counter means providing a count of the number of clock pulse counts during said sampling pulse,
• second subtractor circuit means subtracting the output of said first subtractor circuit from the output of said third counter means, and
• means connecting the output of said second subtractor circuit means to said divider circuit such that upon termination of said sampling pulse the output of said first counter is divided by the output of said second subtractor circuit means to produce a digital signal representing engine rotational speed.

In a control system for an engine including a high speed clock and means producing a sampling pulse, a speed signal producing circuit comprising:

• means including a synchronizing circuit and engine-driven means producing a series of sharp reset pulses whose frequency varies directly with rotational speed of said engine,
• first and second counters connected to said synchronizing circuit and said high speed clock, respectively, such that the initiation of said sampling pulse enables said synchronizing circuit to conduct reset pulses to said first and second counters, receipt of each said reset pulse by said second counter causing said counter to be reset to zero and begin counting high speed counts anew, and said first counter counts said reset pulses,
• first and second memory means connected to said second counter with said first memory means connected to accumulate and hold clock counts occurring between the initiation of said sampling pulse and the previous reset pulse and said second memory means connected to accumulate and hold clock counts occurring between the termination of said sampling pulse and the previous reset pulse,
• and signal processing means including counter means providing a count of the number of clock pulse counts during said sampling pulse for providing a digital signal representing engine rotational speed according to the relationship:
• ##EQU2## where RPM=engine revolutions per minute
• TCT=the number of tooth counts (reset pulses) per sampling pulse
• P.sub.R =the number of tooth pulses per revolution (a constant)
• IT=the period of the sampling pulse in seconds
• T.sub.V =the period of the high speed clock in seconds
• VCT.sub.i =the number of high speed counts in said second memory means, and
• VCT.sub.i-1 =the number of high speed counts in said first memory means.

A speed measurement system for measuring rotational speed of a rotating member including a high speed clock and means producing a sampling pulse, said system comprising:

• means rotatable in proportion to the rotational speed of said rotating member producing signal proportional to the speed of said rotating member,
• a synchronizing circuit connected to receive said signal and to convert said signal to a series of sharp reset pulses of the same frequency as said signal,
• first and second counters connected to said synchronizing circuit and said high speed clock, respectively, such that the initiation of said sampling pulse enables said synchronizing circuit to output reset pulses to said first and second counters, receipt of each of said reset pulses by said second counter causing said counter to be reset to zero and begin counting high speed counts anew, and said first counter counts said reset pulses,
• first and second memory means connected to said second counter with said first memory means connected to accumulate and hold clock counts occurring between the initiation of said sampling pulse and the previous reset pulse and said second memory means connected to accumulate and hold clock counts occurring between the termination of said sampling pulse and the previous reset pulse,
• first subtractor circuit means connected to said first and second memory means producing an output representing the difference in counts contained in said first and second memory means,
• a divider circuit connected to said first counter and means responsive to the termination of said sampling pulse to transfer the counts of said first counter to said divider circuit,
• third counter means providing a count of the number of clock pulse counts during said sampling pulse,
• second subtractor circuit means subtracting the output of said first subtractor circuit from the output of said third counter means, and
• means connecting the output of said second subtractor circuit means to said divider circuit such that upon termination of said sampling pulse the output of said first counter is divided by the output of said second subtractor circuit means to produce a digital signal representing rotational speed of said rotating member.

In a system for controlling the speed of a rotating member including a high speed clock and means producing a sampling pulse, a speed signal producing means comprising:

• first means including a synchronizing circuit and means rotatable with said rotating member producing a series of sharp reset pulses whose frequency varies directly with the speed of said rotating member,
• first and second counters connected to said synchronizing circuit and said high speed clock, respectively, such that the initiation of said sampling pulse enables said synchronizing circuit to conduct reset pulses to said first and second counters, receipt of each said reset pulse by said second counter causing said counter to be reset to zero and begin counting high speed counts anew, and said first counter counts said reset pulses,
• first and second memory means connected to said second counter with said first memory means connected to accumulate and hold clock counts occurring between the initiation of said sampling pulse and the previous reset pulse and said second memory means connected to accumulate and hold clock counts occurring between the termination of said sampling pulse and the previous reset pulse, and
• signal processing means including counter means providing a count of the number of clock pulse counts during said sampling pulse for providing a digital signal representing engine rotational speed according to the relationship:
• ##EQU3## where RPM=revolutions per minute of the rotating member
• TCT=the number of reset pulses per sampling pulse
• P.sub.R =the number of reset pulses per revolution of the rotating member (a constant)
• IT=the period of the sampling pulse in seconds
• T.sub.V =the period of the high speed clock in seconds
• VCT.sub.i =the number of high speed counts in said second memory means and
• VCT.sub.i-1 =the number of high speed counts in said first memory means.

A method of measuring the rotational speed of an apparatus, said method comprising the steps of:

• generating a tooth count signal as a series of pulses, said tooth count signal having each pulse synchronously generated with one of the state transitions of a square wave signal;
• generating an interval signal of a predetermined time period;
• generating a high speed clock gin signal of a substantially higher frequency than said square wave;
• counting the number of tooth count pulses of said tooth count signal occurring within said interval time period, thereby providing a tooth count;
• dividing said tooth count by a number representative of the tooth count of a single revolution of the apparatus, thereby calculating the number of revolutions of the apparatus represented by said tooth count;
• counting the number of high speed clock pulses occurring between the initiation of said interval time period and the first tooth count pulse prior to said initiation wherein that count is termed the T.sub.i-1 count;
• counting the number of high speed clock pulses occurring between the termination of said interval time period and the first tooth count pulse prior to said termination wherein that count is termed the T.sub.1 count;
• counting the number of high speed clock pulses occurring during said interval time period wherein that count is termed the IT count;
• forming the summation of counts IT+(Ti-1)-T.sub.i wherein that count is termed the interval count;
• multiplying the interval count by the period of the high speed clock to yield an accurate time interval T over which said tooth count has occurred;
• and
• dividing the number of revolutions represented by said tooth count by the time interval T to yield a speed signal which is an accurate measurement of the rotational speed of the member.