Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
AssigneeBell Telephone Laboratories, Incorporated
InventorsEliezer Kinsbron, William T. Lynch
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Abstract
This invention involves the defining of a submicron feature (21 or 93) in a structure, typically an insulated gate field effect transistor structure (30, 40, or 110). This feature is defined by a sidewall oxide protective masking layer (21 or 71) formed by reactive oxygen ion etching of the structure being built at a time when an exposed surface thereof in the vicinity of the sidewall contains atoms of a material--for example, silicon or aluminum--which combine with the oxygen ions to form the sidewall oxide layer.
Claims16
A method for fabricating a semiconductor structure comprising the steps of forming, overlying a horizontal surface in a structure, a patterned layer having a vertical sidewall at the bottom of which is located an exposed surface of a first layer of first material, said first material containing atoms of a first kind, and forming on the vertical sidewall a masking layer of predetermined submicron horizontal thickness dimension, and using the masking layer to define a feature of the structure underlying the masking layer,
- the masking layer being formed by bombarding said horizontal surface portion with oxygen for a predetermined time to react with atoms of said first material, located at the exposed surface of the first layer, whereby the masking layer, comprising a chemical compound of oxygen and said atoms, is deposited on the vertical sidewall to the predetermined submicron thickness, and whereby the thickness of the first layer is reduced.
A method for forming a submicron feature by forming a sidewall oxide layer on a vertical sidewall of a first layer of first material located on a limited portion of a second layer of second material, different from the first, said second layer located over a horizontal major surface of a semiconductor body, comprising a first step of reactive ion etching said second layer to form by back-sputtering of said second material a sidewall oxide layer on the vertical sidewall of the first layer whereby the thickness of the second layer is reduced by said reactive ion etching, and a second step of using said sidewall oxide layer as a protective mask for defining said feature.
A method for fabricating an insulated gate field effect transistor in which a gate oxide layer is grown on a major horizontal surface of a silicon body and a polycrystalline silicon gate electrode having a vertical sidewall is formed on a limited portion of the surface of the gate oxide layer comprising the step of forming an insulating layer of predetermined thickness on said sidewall by subjecting an exposed portion of the gate oxide layer, complementary to said limited portion, to reactive ion etching with oxygen to expose the major surface of the body underlying said complementary portion, and whereby the thickness of the exposed portion of the gate oxide layer is reduced.
Dependencies are inferred from the claim text.