Multiport programmable digital data set

Apparatus for transferring data between a plurality of digital data terminals (700) and a transmission medium (800) comprising:

• a digital signal processor (200) for performing a plurality of data set functions which collectively implement at least first and second types of data transfer arrangement;
• a cyclic processor (100) arranged to store a plurality of sequences of instructions, each of which enable said digital signal processor to perform an associated one of said plurality of functions when said instruction sequence is executed by said processor;
• means (300) for sequentially coupling signals originating in each of said data terminals to said digital signal processor for transfer to said transmission medium in accordance with a selected one of said transfer arrangements;
• and
• means (400) for coupling signals from said transmission medium to said digital signal processor for sequential transfer to each of said data terminals in accordance with a selected one of said transfer arrangements.

A digital signal processor arranged to interconnect at least one data terminal with a corresponding transmission path, said data terminal arranged to transmit and receive digital information and said transmission path arranged to carry analog signals modulated by digital information, said processor including:

• (a) means for modulating said digital information transmitted by said data terminal prior to application to said transmission path, and
• (b) means for demodulating said modulated signals to recover said digital information received by said data terminal, CHARACTERIZED IN THAT said modulating and demodulating means includes:
• (c) a high-speed digital processor for performing various arithmetic functions on said signals, and
• (d) a cyclic processor containing an alterable memory adapted to control the sequence and nature of the operations performed by said high-speed processor in accordance with user defined inputs.

A data set comprising:

• a digital buffer processor for coupling said data set to a local data terminal,
• an analog buffer processor for coupling said data set to an analog transmission medium,
• a high-speed digital signal processor responsive to said analog and digital buffer processors, for modulating signals received in said data set from said local terminal and destined for said transmission medium and for demodulating signals received in said data set from said transmission medium and destined for said data terminal, and
• a low-speed cyclical processor for controlling the modulation and demodulation performed by said high-speed processor in accordance with a predefined sequence of stored instructions.

A universal data set (FIGS. 1 and 4) for two-way exchange of digital information between a plurality of data communications terminals (700) and remote terminals connected to said data set via an analog transmission medium (800) employing carrier signal waves and having at least as many channels as there are data terminals comprising:

• a digital buffer processor (300) connected to and interacting with one or more of said terminals (700) for storing samples of digital data signals in the alternative incoming to or outgoing from one or more of said terminals (700);
• an analog buffer processor (400) connected to said transmission medium (800) for converting in the alternative digitally processed outgoing data signals into analog form and analog incoming data signals into digital samples;
• a digital processor (200) responsive to buffered samples of outgoing data signals from said terminals (700) and to digitized analog signals from individual channels in said medium (800) for modulating a carrier signal in accordance with outgoing data signals and for demodulating a modulated carrier signal to recover signals incoming from channels in said medium;
• and
• a cyclic processor (100) for storing predetermined program instructions for controlling the sequencing of said digital processor (200) to effect one or more modulation or demodulation formats;
• said digital processor (200) further comprising first (210) and second (220) bus lines;
• an arithmetic logic unit (230) bridging said bus lines (210, 220) for performing additive and logic operations on signals appearing on said bus lines and delivering the result to one or the other of said bus lines under the control of said cyclic processor (100);
• and
• memory means (250, 260) bridging said bus lines (210, 220) for storing intermediate results of mathematical and logic operations of said arithmetic logic (230) and multiplier (240) units on said signal samples.