Digital phase-locked loop circuit

A digital phase-locked loop for controlling a digital output signal having time periods to track both as to its frequency and its phase a digital input signal having successive time intervals which defines a transmission frequency for said input signal, said input signal being in one of two possible logic states in each time interval, comprising:

• (a) a phase detector responsive to said input and output signals, for detecting in the time intervals the phase difference therebetween;
• (b) a microprocessor responsive to the detected phase differences for generating for each interval a frequency select code to control the frequency of said output signal, the frequency select code for each interval including a phase shift correction component generated only from the measured phase difference for that interval if a phase difference measurement is obtained and a frequency correction component generated from all the measured phase differences;
• and
• (c) a binary rate multiplier responsive to the frequencies select code, for generating said output signal, the frequency select codes generated by said microprocessor controlling the frequency of said output signal on an interval-by-interval basis to cause the phase difference detected in successive intervals by said phase detector to approximate zero thereby locking the phase and frequency of said output signal to the phase and transmission frequency of said input signal.