Processes for manufacturing insulated-gate semiconductor devices with integral shorts

A self-aligned process for manufacturing an insulated-gate semiconductor device including an integral short, said process comprising:

• providing a semiconductor wafer including a first region of one conductivity type having a principal surface, and preparing the wafer by forming on the principal surface a gate insulating region layer, forming on the gate insulating region layer a conductive gate electrode layer, and forming on the conductive gate electrode layer an overhang layer;
• forming an etch resist mask having openings defining the ultimate location of upper electrode regions, and then etching in areas defined by the mask openings through the overhang layer and through the conductive gate electrode layer at least to the gate insulating region layer, with lateral etching of the conductive gate electrode layer to undercut the overhand layer, thereby defining gate electrodes extending upwardly from and spaced along the first region principal surface, with overhanging portions of the overhang layer on the upper surfaces of the gate electrodes;
• oxidizing at least the conductive gate electrode sidewalls;
• introducing into the first region between the gate electrodes impurities appropriate to form a base region of opposite conductivity type and an upper electrode region of the one conductivity type within the base region, the gate electrodes serving as masks during the introduction of impurities, and diffusing the impurities introduced to appropriately locate and configure the base and upper electrode regions such that at the principal surface the base region exists as a band of opposite conductivity type between the upper electrode region and the first region, with active portions of the band underlying at least a portion of at least one gate electrode and being separated therefrom by portions of the gate insulating region layer;
• forming a shorting extension of the base region up through and to a portion of the surface of the upper electrode region intermediate and spaced from the gate electrodes to facilitate an ohmic connection between the base and upper electrode regions, the forming of the shorting extension being accomplished by employing the overhang of the overhang layer as a mask to define said portion of the surface of the upper electrode region;
• and
• forming a metallized gate terminal in electrical contact with the conductive gate electrodes, and forming a metallized upper electrode region terminal in electrical contact with the upper electrode region and with the shorting extension.