Interface for data communication systems using serial biphase data transmissions

An interface for data communication systems using biphase serial transmissions to communicate between a central control unit and a peripheral device, said interface comprising:

• voltage level converter means for converting serial biphase data transmissions from the control unit to serial TTL compatible data;
• sequencer means including a programmable memory having a plurality of address input lines and a plurality of data output lines, operative to step through a sequence of memory addressing steps and provide a preselected code on its data output lines for a given code on its address input lines as a function of the contents of the memory location addressed;
• means for coupling the output of the voltage level converter to at least one address input line of the memory;
• clock means for generating a sequencer clock pulse at least once during each half-bit of the biphase data transmission;
• means for coupling the sequencer clock pulses to the sequencer so that each memory addressing step occurs at substantially the half-bit biphase data transmission rate;
• serial to parallel shift register means having an input coupled to the output of the voltage level converter, operative to sequentially load parallel storage locations with a signal level corresponding to the signal level at its input at the time a shift register clock signal is received at a clock input thereof;
• means for coupling at least one of the memory data output lines to the clock input of said shift register, said memory being adapted to generate shift register clock signals on said data output line when given memory locations have been addressed after said sequencer has progressed through a given sequence of memory addressing steps, said shift register clock signals being generated during one half of the biphase bit time whereby each serial biphase data word is converted into a TTL compatible parallel data word;
• and
• means for coupling the output of the shift register to the peripheral device.

An interface for data communication systems using biphase serial transmissions to communicate between a central control unit and a peripheral device, said interface comprising:

• parallel to serial shift register means for temporarily storing a parallel data word from the peripheral device;
• sequencer means including a programmable memory having a plurality of address input lines and a plurality of data output lines, operative to step through a sequence of memory addressing steps and provide a preselected code on its data output lines for a given code on its address input lines as a function of the contents of the memory locations addressed;
• means for coupling a serial output line of the shift register means to at least one address input line of the memory;
• clock means for generating sequencer clock pulses at substantially the half-bit biphase data transmission rate;
• means for coupling the sequencer clock pulses to the sequencer so that each memory addressing step occurs at the half-bit biphase data transmission rate;
• said sequencer being operative to provide on one of said memory output lines a serial biphase data word corresponding to the parallel data word in said shift register;
• and
• means for coupling the biphase serial data word to the control unit.

An interface for data communication systems using biphase serial transmissions to communicate between a central control unit and a peripheral device, said interface comprising:

• a programmable read only memory with a plurality of address input lines and a plurality of data output lines;
• multibit latch means having a plurality of input lines a subset of which are coupled to a subset of the data output lines from the memory, said latch having a plurality of data output lines;
• means for feeding back a subset of the latch output lines to selected address input lines of the memory;
• voltage level converter means for converting serial biphase data transmissions from the control unit to serial TTL compatible data;
• a dual mode serial in-parallel out/parallel in-serial out shift register means having a serial input, a serial output, a group of parallel input/output lines and a clock input;
• first multiplexor means for selectively coupling the output of said voltage level converter and said serial output of said shift register to a selected address input line of the memory;
• receiver clock means for generating a clock pulse at least once during each half-bit of the biphase data transmission received from the control unit;
• transmitter clock means for generating clock pulses at substantially the half bit transmission rate;
• second multiplexor means for selectively coupling said receiver clock and transmitter clock to a clock input of said latch to thereby control the timing of each memory addressing step;
• means for coupling a selected data output line from the memory of the clock input of said shift register;
• means for controlling said first and second multiplexors depending upon whether data is being received or transmitted;
• and
• whereby said voltage level converter is coupled to the memory and the receiver clock is coupled to the latch when serial biphase transmissions are received from the control unit to thereby generate TTL compatible parallel data on the group of shift register input/output lines for use by the peripheral, and wherein the serial output of the shift register is coupled to the memory and the transmitter clock is coupled to the latch means when TTL compatible data from the peripheral is supplied to the group of shift register input/output lines to thereby generate serial biphase data for transmission back to the control unit.

A receiver clock generator circuit for providing clock pulses to components of an interface circuit in synchronism with biphase serial data transmissions from a central control unit, said circuit comprising:

• voltage level converter means for converting said biphase transmissions to a first series of TTL compatible level signals;
• delay means for delaying the converted TTL signals for a period substantially less than a predefined half-bit time for the biphase transmissions thereby providing a second series of TTL level signals;
• comparator means for comparing said first and second series of TTL level signals, operative to provide a pulse when the signals are different;
• counter means having a reset input coupled to the output of said comparator means, operative to provide an output pulse after a given time period unless reset by a pulse from said comparator means;
• and
• means for combining the pulses from the comparator means and the counter means to provide clock signals for the interface, said clock signals being derived from the comparator means when there is a transition of the signal level in the biphase transmissions and being derived from the counter means when such transitions do not occur at regularly spaced time intervals.

A waveform generator for converting TTL serial data signals from an interface into biphase serial data signals having perscribed waveforms for transmission to a central control unit, said waveform generator comprising:

• first transistor means for providing positive signal levels;
• second transistor means for providing negative signal levels;
• logic network means for placing said first transistor into saturation for about a quarter of a preselected bit time whenever there is a positive going transition of the TTL signals thereby providing a positive predistortion pulse, said logic network means being further operative to place said first transistor into its forward activate region for generating a given positive signal level until there is a negative going transaction of the TTL signals;
• and
• said logic network means being further operative to place said second transistor into saturation for about a quarter of the bit time whenever there is a negative going transition of the TTL signals thereby providing a negative predistortion pulse, said logic network means being also adapted to place said second transistor into its forward active region to provide a given negative signal level until there is a positive going transition of the TTL signals.