Power and ground plane structure for chip carrier
AssigneeAMP Incorporated
InventorDimitry G. Grabbe
Life of this patent
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Abstract
A chip carrier having a plurality of leads thereon for external interconnection with preferably only one of the leads utilized to provide a source of power to the chip and preferably a single lead utilized as a ground connection. The power and ground leads are connected in a bus structure around the chip at the center of the chip carrier with the chip being secured to the chip carrier with the bus structure over a thermal pad formed within the bus structure. A decoupling capacitor is located in close proximity to the chip on the substrate to assure low reaction due to switching.
Claims2
A system for carrying semiconductor chips and the like comprising:
- (a) an electrically insulating ceramic substrate,
- (b) a copper electrical conductor pattern having a copper oxide surface adjacent said substrate and fused to said substrate, said conductor pattern extending to plural locations at the edges of said substrate,
- (c) an electrically and thermally conductive pad at the center of said substrate for receiving a semiconductor chip thereon,
- (d) a first electrically conductive pattern on said substrate surrounding said pad and connected to a lead of said conductor pattern, and
- (e) a second electrically conductive pattern on said substrate surrounding said pad within said first conductive pattern and connected to a lead of said conductor pattern.
Dependencies are inferred from the claim text.