Macroinstruction translator unit for use in a microprocessor

For use in a data processing system including a main memory for storing macroinstructions, said macroinstructions including a field specifying either a first executable operation requiring a single microinstruction to execute, or a second executable operation requiring a series of microinstructions to execute, and an execution unit for executing said microinstructions, a microprocessor instruction unit comprising:

• an instruction decoder for receiving macroinstructions from said main memory;
• said instruction decoder including means for interpreting said field of said macroinstructions to provide first signals indicating that said field specifies said first executable operation requiring a single microinstruction to execute, or that said field specifies said second executable operation requiring a series of microinstructions to execute,
• said instruction decoder including first means connected to said interpreting means and responsive to said second signals for generating starting addresses for microinstruction routines, said microinstruction routines being comprised of a series of microinstructions, and,
• said instruction decoder including second means connected to said interpreting means and responsive to said first signals for generating single microinstructions;
• said instruction decoder including control means connected to said interpreting means and to said first and second means for activating said first means or said second means to thereby cause starting addresses or single microinstructions to be generated in response to said second or first signals, respectively;
• a microinstruction sequencer for sequencing through said series of microinstruction comprising said microinstruction routines;
• said microinstruction sequencer including third means connected to said first means for receiving said starting addresses for said microinstruction routines,
• said microinstruction sequencer including fourth means connected to said second means for receiving said single microinstructions,
• said microinstruction sequencer including fifth means connected to said third and fourth means for decoding said microinstructions, and
• said microinstruction sequencer including sixth means responsive to said fifth means for transferring microinstructions to said execution unit;
• microinstruction sequencer control means;
• a first-in, first-out buffer connected between said second means and said fourth means for buffering single microinstructions received from said second-generating means;
• seventh means connected to said instruction decoder and to said first-in first-out buffer for transferring said single microinstructions from said second means to said first-in, first-out buffer under control of said instruction decoder control means;
• eighth means connected to said microinstruction sequencer and to said first-in first-out buffer for transferring said single microinstructions from said first-in, first-out buffer to said fourth means under control of said microinstruction sequencer control means;
• said first-in, first-out buffer including a flag bit, said flag bit being settable to a first state by said seventh means to indicate that said first-in, first-out buffer is full, and said flag bit being resettable to a second state to indicate that said first-in, first-out buffer is not full;
• ninth means connected to said instruction decoder and to said flag bit for setting said flag bit;
• and
• tenth means connected to said microinstruction sequencer control means and to said flag bit for resetting said flag bit.