US 4,413,239 AGranted

Field effect transistor circuit for modulator and demodulator applications

AssigneeThe United States of America as represented by the Secretary of the Navy

InventorsDonald E. Romeo, George W. McIver

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Abstract

A double balanced modulator-demodulator consisting of two pairs of field ect transistors. A field effect transistor is connected in series between the source electrodes of each of the field effect transistor pairs. The field effect transistors making up each pair are biased so that they operate in the saturated mode. Each of the transistors connected between the source electrodes of the transistor pairs are biased to operate in the linear mode such that drain current varies linearly with drain voltage. A first input signal is connected across the gate electrodes of the transistor pairs while a second input signal is connected across the gate electrodes of the connecting transistors. Bias for each of the transistor pairs is provided by means of a field effect transistor connected between the source electrodes of the transistor pairs and ground. The gates and source electrodes of transistors forming the bias circuit are connected to ground. The outputs of the two pairs are connected in parallel such that the differential output current is proportional to the product of the input signals.

Claims2

Dependent claims

Apparaus for producing a signal proportional to the product of two differential input signals comprising:

first and second pairs of field effect transistors,
each of the field effect transistors of said first and second pairs having gate, source and drain electrodes,
a first series connected field effect transistor having a source electrode and a drain electrode connected in series between the source electrodes of one of said pairs of field effect transistors and having a gate electrode,
a second series connected field effect transistor having a source electrode and a drain electrode connected in series between the source electrodes of the other of said pairs of field effect transistors and having a gate electrode,
said source electrodes of said pairs of field effect transistors being held at a common reference potential,
means for applying a first differential input signal across the gate electrodes of each of said pairs in
parallel,
means for applying a second differential input signal across the gate electrodes of said first and second series connected field effect transistors, and
loading circuit means connected to the drain electrodes of said pairs of field effect transistors for providing an output signal proportional to the product of said first and second differential input signals.

6 more elements

Dependencies are inferred from the claim text.