Distributed signal processing system

In combination:

• a plurality of distributed signal processing systems;
• each of said systems comprising a plurality of elements including a signal processor, a mass memory and an input-output controller, and a first bus means for interconnecting in common said plurality of elements;
• said input-output controller of each one of said systems comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices;
• each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously;
• and
• said signal processor comprising operating means for managing processing tasks within said plurality of elements and systems.

In combination:

• a plurality of distributed signal processing systems;
• each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements;
• each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices;
• and
• each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously.

In combination:

• a plurality of distributed signal processing systems;
• each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements;
• each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices;
• each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously;
• each of said elements comprising means for detecting a faulty element;
• and
• self-repair means for correcting said faulty element by removing said faulty element from operating service and replacing said faulty element with a similar spare element.

In combination:

• a plurality of distributed signal processing systems;
• each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements;
• each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems and by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices;
• each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously;
• each of said elements comprising means for detecting a faulty element;
• self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element;
• and
• said signal processors comprising distributed operating system means for managing processing tasks and self-repair means within said plurality of elements and systems.

In combination:

• a plurality of distributed signal processing systems;
• each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault-tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements;
• each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling of a plurality of input-output data devices;
• each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously;
• each of said elements comprising means for detecting a faulty element;
• self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element;
• and
• a distributed operating system means in said signal processors for managing said plurality of elements comprising a local level segment of said distributed operating system, DOS-0, for performing individual signal processor management and fault monitoring, and a system level segment of said distributed operating system, DOS-1, for performing system task management, fault monitoring and self-repair.

In combination:

• a plurality of distributed signal processing systems;
• each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers, and a first bus means for interconnecting in common said plurality of elements;
• each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices;
• each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously;
• each of said elements comprising means for detecting a faulty element;
• self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element;
• said signal processors comprising distributed operating system means for managing processing tasks and self repair means within said plurality of elements and systems;
• and
• arithmetic means in each of said signal processors for performing multiplication and addition operations simultaneously within a single clock cycle time period of said signal processors.

In combination:

• a plurality of distributed signal processing systems;
• each of said systems comprising a plurality of elements including a plurality of signal processors, a plurality of mass memories and a plurality of input-output controllers for fault tolerant operation capability, and a first bus means for interconnecting in common said plurality of elements;
• each one of said input-output controllers comprising a second bus means for interconnecting a plurality of said systems by coupling said second bus means of one of said systems to said first bus means of another of said systems and for providing coupling to a plurality of input-output data devices;
• each of said elements comprising one or more bus transceivers and arbitration means coupled to one of said first and second bus means for determining the one of a plurality of elements connected to said one of the first and second bus means that obtains first use of said connected one of the first and second bus means when more than one of said elements attempt to use one of said first and second bus means simultaneously;
• each of said elements comprising means for detecting a faulty element;
• self-repair means comprising an element address register in each of said elements for removing said detected faulty element from operating service and replacing said faulty element with a spare element;
• a distributed operating system means in said signal processors for managing said plurality of elements comprising a local level segment of said distributed operating system, DOS-0, for performing individual signal processor management and fault monitoring, and a system level segment of said distributed operating system, DOS-1, for performing system task management, fault monitoring and self-repair;
• OPERATE instruction means comprising instructions for performing control operations between an application program and said local level segment, DOS-0, of said distributed operating system, for performing complex signal processing operations including a multiplication of two complex matricies, and a radar target detection and clutter map update calculation and for performing logic and memory diagnostic tests.

In a network comprising a plurality of distributed signal processing systems each of said systems comprising a plurality of elements, the method of determining which one of said elements becomes an executive containing a system level segment of a distributed operating system, DOS-1, comprising steps of:

• performing self-test programs located in a local level segment, DOS-0, of said distributed operating system in a signal processor when power is applied;
• sending a "ready and executive request" message from said signal processor to a mass memory after the successful completion of said self-test programs;
• performing bus arbitration if two or more of said signal processors try to use a bus simultaneously for sending said "ready and executive request" message;
• and
• preventing more than one signal processor from obtaining said executive of said distributed operating system, by changing the address of said mass memory as soon as said mass memory receives said first "ready and executive request" message resulting in said other signal processors entering an idle state until assigned a task by said executive.

In combination

• a plurality of elements;
• said plurality of elements comprising a signal processor, a mass memory and an input-output controller;
• first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system;
• a plurality of said distributed signal processing system forming a network comprising a second bus interconnecting means between said input-output controller of one of said systems and said first bus means of another of said systems;
• means for communicating between said systems by at least two separate busses;
• and
• said plurality of systems comprising means in at least one element for performing self-repair of said network.

In combination:

• a plurality of elements;
• said plurality of elements comprising a signal processor, a mass memory and an input-output controller;
• first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system;
• a plurality of said distributed signal processing systems forming a network comprising a second bus interconnecting means between said input-output controller of one of said systems and said first bus means of another of said systems;
• means for communicating between said systems by at least two separate busses;
• means for communicating with a plurality of input-output data devices by at least two separate busses;
• said plurality of systems comprising means in at least one element for performing self-repair of said network;
• and
• said input-output controller comprising a plurality of operating modes including a bus extended mode for communicating between said interconnected systems, and a dynamic input-output mode for communicating with said input-output data devices coupled to said controller.

In combination:

• a plurality of elements;
• said plurality of elements comprising a signal processor, a mass memory and an input-output controller;
• first bus means for interconnecting in common said plurality of elements to form a distributed signal processing system;
• a plurality of said distributed signal processing systems forming a network comprising a second bus interconnecting means between said input-output controller bus means of another of said systems;
• means for communicating between said systems by at least two separate busses;
• means for communicating with a plurality of input-output data devices by at least two separate busses;
• said plurality of systems comprising means in at least one element for performing self-repair of said network;
• said input-output controller comprising a plurality of operating modes including a bus extended mode for communicating between said interconnected systems, and a dynamic input-output mode for communication with said input-output data devices coupled to said controller;
• and
• means for managing said network comprising a distributed operating system.