Flicker preventing circuit

A flicker preventing circuit for a television receiver which displays interlaced even and odd video fields during successive field periods in response to an input video signal, each of said fields comprising a plurality of horizontal lines displayed during successive horizontal periods, said circuit comprising:

• delay means receiving said input video signal and providing therefrom first and second delayed signals which are delayed by one horizontal period and by two horizontal periods, respectively, relative to said input video signal;
• processing means receiving said input video signal and said first and second delayed signals and including means for alternatively delivering said input video signal and said second delayed signal during successive field periods, as a first output of said processing means, and delivering said first delayed signal as a second output of said processing means, with the level of said first output being different from the level of said second output;
• and
• adding means for adding said first and second outputs of said processing means and providing a corresponding sum signal as the output of said flicker preventing circuit.