Dual mode tone detector circuit
AssigneeMotorola, Inc.
InventorLawrence M. Ecklund
Life of this patent
Estimating the term…
Abstract
A low frequency tone detector filters out undesired frequencies in a received signal, than a latching circuit locks on when a given number of low frequency cycles are detected, having at least a predetermined peak amplitude. Thereafter, only a second given number of missing or low amplitude cycles will reset the latch. When the detector determines that the received signal is weak or of very poor quality, false detect signals are essentially prevented. The circuit is particularly suited to use with AM stereophonic signals where a low frequency tone is added to the difference channel for providing mono/stereo indication and mode switching.
Claims11
Dual mode tone detector means comprising:
- input means for receiving signals which may include one signal of a predetermined frequency;
- filter means coupled to the input means for outputting only those received signals at or near the predetermined frequency;
- first circuit means coupled to the filter means output and including comparator means for determining the peak amplitude of each filtered signal cycle, shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said signal frequency, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said signal frequency having an absolute value less than the predetermined peak amplitude;
- second circuit means coupled to the shift register means outputs and the logic means output and including timing means for providing a timed output signal of a predetermined period in response to the reception of the second predetermined number of consecutive cycles having an absolute value less than the predetermined peak amplitude, said second predetermined number of cycles following at least one cycle having at least the predetermined peak amplitude and gating means;
- and
- means coupled to the first and second circuit means and responsive to the first and second output signals, the gating means decoupling the responsive means from the logic means during said timed output signal.
A receiver for receiving a carrier wave which is modulated with signal information proportional to M+N where M is the amplitude of an intelligence signal and N is the amplitude of an indicator signal, the receiver comprising in combination:
- means for selectively receiving the modulated carrier wave;
- means for translating the received carrier wave to one of an intermediate frequency;
- circuitry coupled to the translating means for providing an output signal proportional to M;
- filter means coupled to the translating means for outputting only those signals at or near the frequency of said indicator signal;
- first circuit means coupled to the filter means output and including comparator means for determining the peak amplitude of each detected cycle;
- shift register means coupled to the comparator means, and logic means coupled to the shift register means outputs for providing a first output signal only in response to the reception of a first predetermined number of consecutive cycles of said signal frequency, each said cycle having at least a predetermined peak amplitude, and a second output signal only in response to the reception of a second predetermined number of consecutive cycles of said signal frequency having an absolute value less than the predetermined peak amplitude;
- second circuit means coupled to the shift register means outputs and the logic means output and including timing means for providing a timed output signal of a predetermined period in response to the reception of the second predetermined number of consecutive cycles having an absolute value less than the predetermined peak amplitude, said second predetermined number of cycles following at least one cycle having at least the predetermined peak amplitude and gating means for decoupling the responsive means from the logic means during said timed output signal.
Dependencies are inferred from the claim text.