Process control computer wherein data and addresses are separately processed

A sequentially pulse-frequency driven process control computer, comprising

• a data input/output unit;
• an address memory;
• a separate address processor;
• an address bus;
• a main memory directly connected to said data input/output unit and, via said address processor and said address bus, to said address memory;
• a program memory;
• a clock generator connected to said program memory and said address memory and supplying sequential clock pulses for the execution of the program and for the simultaneous delivery of addresses in each program step;
• a data bus separate from said address bus;
• an arithmetic logic unit, said main memory storing the data from said data-output unit after the feeding of the addresses from said address processor supplying the data for the program step to said arithmetic logic unit via said data bus, said arithmetic logic unit simultaneously receiving pulse-frequency driven operation commands from said program memory and feeding the operation results via said data bus to said data input/output unit and to said main memory for storing;
• and
• a program step counter connected to said program memory and continuing switching of the program steps and controlling the output of the operation commands from said program memory.