Monolithic integration of logic, control and high voltage interface circuitry
AssigneeTexas Instruments Incorporated
InventorPatrick A. Curran
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Abstract
Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.
Claims5
A process for the monolithic integration of a semiconductor circuit having D-MOS and high performance vertical NPN components, comprising the steps of:
- (a) providing a monocrystalline p-type semiconductor substrate having a surface layer of isolated n-type semiconductor regions thereon;
- (b) forming a lightly-doped p-type D-well region in each of selected said n-type regions;
- (c) forming p-type regions constituting the vertical NPN base and the D-MOS gate contact;
- (d) then selectively forming n-type regions constituting the vertical NPN emitter and collector;
- and
- (e) controlling the dopant concentration in step (b) such that said D-MOS threshold is determined by the intersection of said emitter and said D-well dopant profiles.
A process for the monolithic integration of a semiconductor circuit having D-MOS and high performance vertical NPN components, comprising the steps of:
- (a) providing a monocrystalline p-type semiconductor substrate having a surface layer of isolated n-type semiconductor regions thereon;
- (b) forming a lightly-doped p-type D-well region in each of selected n-type regions;
- (c) forming p-type regions constituting the vertical NPN base and the D-MOS gate contact;
- (d) selectively opening windows in a mask and forming D-MOS drain and NPN collector contacts;
- and
- (e) then selectively opening windows in said mask and forming the NPN emitter and D-MOS source, in order to reduce mask undercutting and preserve D-MOS alignment.
A process for the monolithic integration of a semiconductor circuit having a D-MOS component and a vertical bipolar component with independently controlled characteristics, comprising the steps of:
- (a) providing a monocrystalline semiconductor substrate of one conductivity type having a surface layer of isolated first semiconductor regions of the opposite conductivity type thereon;
- (b) forming a lightly-doped second region of said one conductivity type in each of selected of said first regions;
- (c) forming third regions of said one conductivity type constituting the base region of said bipolar component and the D-MOS gate contact;
- (d) selectively forming fourth and fifth regions of said opposite conductivity type constituting the emitter and collector of said vertical bipolar component;
- and
- (e) controlling the dopant concentration in step (b) such that said D-MOS threshold is determined by the intersection of said emitter and said second region dopant profiles.
Dependencies are inferred from the claim text.