Method of manufacturing a logic circuit including at least one field-effect transistor structure of the normally-off type and at least one saturable resistor

A method of manufacturing a logic circuit having at least one field effect transistor and at least one saturable resistor, comprising:

• forming an active semiconductor layer on a face of a semi-insulating substrate, said active layer formed with a thickness of at least a predetermined value a.sub.1 ;
• depositing simultaneously ohmic contacts to produce source and drain regions for said at least one saturable resistor and said at least one field effect transistor;
• depositing a Schottky contact between the source and drain ohmic contacts of said at least one saturable resistor to form a gate region;
• depositing a metal connection between the source contact and the Schottky contact of said at least one saturable resistor;
• applying a voltage to the source and drain contact of said at least one saturable resistor and then measuring the drain-source current therein to deduce therefrom a measure of the localized thickness of a.sub.1 at the location of the logic circuit including the at least one saturable resistor and the at least one field effect transistor;
• cutting a groove between the source and drain contacts of the at least one field effect transistor to obtain a predetermined channel depth a.sub.o from the bottom of said groove to said semi-insulating substrate, the depth of said groove (a.sub.1 -a.sub.o) being determined by the localized measurement of a.sub.1 from the preceding step;
• and
• depositing a Schottky contact in the groove of said at least one field effect transistor.