# US 4,400,818 A · Rotary switch simulator

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- Number: US 4,400,818 A
- Document ID: US4400818A
- Status: Granted
- Kind: A
- Application number: 06/229,551
- Filed: 1981-01-29
- Granted: 1983-08-23
- Earliest claimed: 1981-01-29
- Assignees: Burroughs Corporation
- Inventors: Ira P. Shapiro
- Web page: https://patentgrep.com/patent/US4400818A

## CPC

- H03K 17/965: Switches controlled by moving an element forming part of the switch
- H03K 17/18: Modifications for indicating state of switch
- H03K 17/6285: {with several outputs only combined with selecting means}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A rotary-type switch simulator includes a shift register and a counter, both clocked by a momentary contact switch. The shift register outputs drive visual indicators indicating the selected switch position, while the counter provides a binary output corresponding to the indicated switch position. Logic circuitry, responsive to selected data bits at the outputs of the shift register and counter, reset the shift register and counter respectively to their initial states after the highest switch position has been accessed.

## Claims

### Claim 1

An apparatus for simulating an n-position rotary-type switch, said apparatus providing an ordered set of n outputs, a next sequential one of said n outputs being selected each time said apparatus is actuated, the sequence of outputs selected being repeated after n actuations of said apparatus, said apparatus comprising:
input means for initiating the actuation of said apparatus to its next sequential position;
shift register means, responsive to said input means, for specifying which one of said n sequential positions is selected; and
enabling means, responsive to the selected one of said n sequential positions from said shift register means, for enabling a preset of said shift register means for subsequently loading a set of preset data into said shift register means upon the n.sup.th actuation of the said input means to repeat the said sequence.

### Claim 2 (depends on 1)

The apparatus in accordance with claim 1 further including a plurality of indicator means, responsive to said shift register means, for visually indicating the selected one of said n sequential positions.

### Claim 3 (depends on 2)

The apparatus in accordance with claim 2 further including counter means, responsive to said input means, for providing a binary coded output corresponding to the selected one of said n-sequential positions.

### Claim 4 (depends on 3)

The apparatus in accordance with claim 3 wherein said counter means includes an m bit binary counter, where 2.sup.m is at least equal to n.

### Claim 5 (depends on 4)

The apparatus in accordance with claim 4 wherein said counter means includes detection means, responsive to said m-bit counter reaching a count corresponding to the value (n-1), for enabling a reset of said counter means to an initial count.

### Claim 6 (depends on 5)

The apparatus in accordance with claim 5 wherein said enabling means is further responsive to a user supplied external input.

### Claim 7 (depends on 5)

The apparatus in accordance with claim 5 wherein said shift register means includes a parallel-access shift register having an n-bit data input and an n-bit data output, said enabling means responsive to the presence of a true bit in the high order bit position of said n-bit data output, said set of preset data including a true bit in its low order bit position.

### Claim 8 (depends on 7)

The apparatus in accordance with claim 7 further including counter means, responsive to said input means, for providing a binary coded output corresponding to the selected one of said n-sequential positions.

### Claim 9 (depends on 8)

The apparatus in accordance with claim 8 wherein said counter means includes an m bit binary counter, where 2.sup.m is at least equal to n.

### Claim 10 (depends on 9)

The apparatus in accordance with claim 9 wherein said counter means includes detection means, responsive to said m-bit counter reaching a count corresponding to the value (n-1), for enabling a reset of said counter to an initial count.

### Claim 11 (depends on 7)

The aparatus in accordance with claim 7 wherein said shift register means, in response to said input means, will shift the contents of said shift register one bit position toward the corresponding high order position of said shift register.

### Claim 12 (depends on 11)

The apparatus in accordance with claim 11 wherein said plurality of indicator means includes n indicator means, each one of said n indicator means responsive to the presence of a true bit in one of the shift register's n-data output bit positions.