# US 4,400,713 A · Matrix array of semiconducting elements

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 4,400,713 A
- Document ID: US4400713A
- Status: Granted
- Kind: A
- Application number: 06/213,288
- Filed: 1980-12-05
- Granted: 1983-08-23
- Earliest claimed: 1979-12-07
- Assignees: International Business Machines Corporation
- Inventors: Michel G. Bauge; Pierre B. Mollier
- Web page: https://patentgrep.com/patent/US4400713A

## CPC

- H03K 19/17708: {using an AND matrix followed by an OR matrix, i.e. programmable logic arrays}
- G11C 17/08: using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence)
- H10B 20/00: Read-only memory [ROM] devices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- Y10S 257/926: Elongated lead extending axially through another elongated lead
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

Integrated matrix array the points of which are defined by the intersection of the parallel lines of a first set with the parallel lines of a second set, said points being provided, or not provided, with semiconducting elements which have a first electrode connected to a line of the first set and a second electrode connected to a line of the second set, the array being of the type in which the first electrodes of the elements in each column or row are defined in a common semiconducting region, the second electrodes being provided only in the positions in which a semiconducting element is to be operative, said array being arranged such that: (a) the semiconducting elements in each column or row are partitioned into groups of 2k elements, (b) in each group, the semiconducting layer is partitioned into two portions, the first portion extending from one end of the group up to the position provided with the semiconducting element which is closest to the middle point of the group, and the second portion extending from the other end of the group up to the position provided with the semiconducting element which is closest to the middle point of the group. (c) connecting means are provided to ensure the electrical connection between the ends of the two portions of the semiconducting layer.

## Claims

### Claim 1

An integrated matrix array of semiconductive elements embedded in a substrate, the points of said array being defined by the intersection of parallel lines of a first set with parallel lines of a second set, said points being provided, or not provided, with said semiconductive elements which have a first electrode connected to a line of a first set and a second electrode connected to a line of a second set, the array being of the type in which the first electrodes of the semiconductive elements in each column or row are defined in a common sub-collector semiconductive region, the second electrodes being defined by contact with an epitaxial layer and provided only in positions in which a semiconductive element is to be operative, said array being arranged such that:
(a) the semiconductive elements in each column or row are partitioned into groups of 2k elements;
(b) in each group, said sub-collector semiconductive region and said epitaxial layer are selectively discontinuous, being partitioned into two portions, the first portion extending from one end of the group to the position having an operative semiconductive element closest to the mid-point of the group, and the second portion extending from the other end of the group to the position having an operative semiconductive element closest to the mid-point of the group;
(c) connecting means extending between said ends of the two portions of said sub-collector semiconductive region in each group of semiconductive elements;
(d) said substrate being of first conductivity-type, and in which in each group, said two portions comprise the semiconductive epitaxial layer and the common sub-collector semiconductive region, both of opposite conductivity-type, both portions being isolated by an isolation region of said first conductivity type.

### Claim 2 (depends on 1)

An array according to claim 1 in which said connecting means include:
(a) first and second metal levels
(b) at both ends of each group of semiconductive elements, an assembly including a contact with the semiconductive region located at said first metal level and a via between said first and second metal levels, the two levels being isolated by a layer of isolating material,
(c) a short cirucit provided at the second metal level between the two contacts at the ends of each group through the vias.

### Claim 3 (depends on 2)

An array according to claim 2, in which the semiconductive elements comprise Schottky diodes in which the first electrodes are defined in the common semiconductive region and the second electrodes, which are selectively present, make up the anodes which are connected to the lines of the second set located at the first metal level.

### Claim 4 (depends on 3)

An array according to claim 3 in which the columns or rows of diodes are isolated from each other by isolation walls of the P+ type.

### Claim 5 (depends on 1)

An array according to claim 1 in which the semiconductive elements are transistors in which the first electrodes are the bases defined in the portions of the common semiconductive regions, the second electrodes which are selectively present, are the emitters which are connected to the lines of the second set located at the first metal level, the collectors of said transistors being connected to a biasing voltage supply.

### Claim 6 (depends on 5)

An array according to claim 5, in which the transistors are of the NPN type and are integrated in a substrate of the P type.

### Claim 7 (depends on 6)

An array according to claim 6, in which each group, both portions of the common semiconductive region have a conductivity of the P type, the emitter regions of the N+ type being diffused into corresponding points of said portions that are to be provided with a semiconductive element, said emitter regions being connected to the lines of the second set.