# US 4,400,689 A · A-to-D Converter of the successive-approximation type

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- Number: US 4,400,689 A
- Document ID: US4400689A
- Status: Granted
- Kind: A
- Application number: 05/931,960
- Filed: 1978-08-08
- Granted: 1983-08-23
- Earliest claimed: 1977-04-07
- Assignees: Analog Devices, Inc.
- Inventors: Adrian P. Brokaw; Modesto A. Maidique
- Web page: https://patentgrep.com/patent/US4400689A

## CPC

- H03M 1/406: {using current mode circuits, i.e. circuits in which the information is represented by current values rather than by voltage values}
- H03M 1/145: {the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

## Claims

### Claim 1

An analog-to-digital converter comprising a single monolithic chip formed with:
a plurality of normal mode transistor current sources arranged to produce respective currents for summation into a composite signal;
I.sup.2 L inverted mode transistor means including logic circuit means defining successive-approximation control means arranged to carry out a successive-approximation algorithm;
switch means comprising a series of individual switch circuits in the form of normal-mode transistors serving to selectively control the outputs of said current sources;
said I.sup.2 L inverted mode transistor means including clock means for supplying clock pulses to said logic circuit means to carry out said successive-approximation algorithm;
said successive-approximation control means comprising a series of register stages which are activated in sequence as the algorithm proceeds;
said register stages comprising I.sup.2 L inverted mode transistors arranged as flip-flops;
means connecting each of said individual switch circuits to a collector of one of said flip-flops without the interposition of level translators therebetween;
the switch circuits being operable in sequence by the collector currents and connected to a corresponding current source to cause current from its source to be supplied to a summing point, whereby the combination of selected currents develops at said summing point said composite signal for comparison with an analog input signal.

### Claim 2 (depends on 1)

A converter as in claim 1, wherein said logic means comprises a clock pulse generator having a plurality of outputs to control the development of said algorithm;
said clock pulse generator comprising inverted mode gate transistors arranged in the form of a ring oscillator operating at a frequency responsive to the gate delay of the inverted-mode gates forming the ring, whereby the oscillator frequency is automatically compensated for variations in gate delay in the associated inverted-mode logic circuitry of the converter, regardless of the cause of such variations.