# US 4,400,637 A · Integrator with sampling stage

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- Number: US 4,400,637 A
- Document ID: US4400637A
- Status: Granted
- Kind: A
- Application number: 06/252,048
- Filed: 1981-04-08
- Granted: 1983-08-23
- Earliest claimed: 1980-04-30
- Assignees: Siemens Aktiengesellschaft
- Inventors: Heinrich Klar; Berward Roessler
- Web page: https://patentgrep.com/patent/US4400637A

## CPC

- G06G 7/186: using an operational amplifier comprising a capacitor or a resistor in the feedback loop
- H03F 3/005: {using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers (H03F3/45 takes precedence)}
- H03F 3/45775: {by using cross switches}
- H03F 3/45968: {by offset reduction}
- H03H 19/004: {Switched capacitor networks}
- H03F 2200/81: Inputs or outputs are crossed during a first switching time, not crossed during a second switching time
- G06G: ANALOGUE COMPUTERS (analogue optical computing devices G06E3/00)
- H03F: AMPLIFIERS
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

An integrator with a sampling stage at the input side has a first capacitor with associated electronic switches and has one or more amplifier stages each having a feedback path containing a second capacitor which is connected to the output of the sampling stage. The integrator has a first polarity commutator interconnected between the output of the sampling stage and the input of the first amplifier stage and a second polarity commutator at the output of one of the amplifier stages, the second polarity commutator being operated synchronously with the first polarity commutator. By periodic actuation of the polarity commutators, the low frequency noise voltage components, having amplitudes which vary minimally within a polarity reversal period, cancel when the integration results of successive periods of opposite polarity are added and are thus substantially eliminated.

## Claims

### Claim 1

An integrator with a switched - capacitor sampling stage at the input of said integrator, said sampling stage having a first capacitor having one lead interconnected between first and second alternatingly opened electronic switches and said integrator having at least one amplifier stage having a feedback path containing a feedback capacitor which is connected to an output of said sampling stage, said integrator further comprising:
a first polarity commutator interconnected between the output of the sampling stage and an input of a first amplifier stage, said first polarity commutator selectively switching the polarity of a first signal supplied from said sampling stage for forming a first commutator output signal which is supplied to said input of a first amplifier stage, the polarity of said first commutator output signal being the same as or the opposite of the polarity of said first signal depending on the switching state of said first polarity commutator;
a second commutator connected to an output of at least one of said amplifier stages for selectively switching the polarity of an amplifier output signal appearing at the output of said one of said amplifier stages, said amplifier output signal being derived from said first commutator output signal through said first amplifier stage and any following amplifier stages including said one of said amplifier stages, said amplifier output signal being transformed by said second polarity commutator for forming a second commutator output signal, the polarity of said second commutator output signal being the same as or opposite the polarity of said amplifier output signal depending on the switching state of said second polarity commutator;
said feedback path being connected to an output of said second polarity commutator for supplying said second commutator output signal to said feedback capacitor; and
a clock means connected to said first and second electronic switches and to said first and second polarity commutators for alternatingly opening and closing said first and second switches for forming a polarity of said first signals, and for operating said first and second polarity commutators for switching the polarities of said first signals and said amplifier output signals derived therefrom for mutually compensating the influences of said first and second polarity commutators on said second commutator output signals, said second commutator output signals being summed by said feedback capacitor for forming an output signal for said integrator such that noise voltages from said first amplifier stage have respective repeatedly switched polarities depending on the sequence of switching states of said second polarity commutator, thereby being substracted from each other by said feedback capacitor so as to be suppressed.

### Claim 2 (depends on 1)

The integrator of claim 1 wherein said second polarity commutator is connected at the output of said first amplifier stage.

### Claim 3 (depends on 1)

The integrator of claim 1 wherein said second polarity commutator is connected to a positive and a negative output of an amplifier stage which is a differential amplifier and to an asymmetrical input of a following amplifier stage, said asymmetrical input being alternatingly connected to one of said positive and negative outputs of said differential amplifier.

### Claim 4 (depends on 3)

The integrator of claim 3 wherein said differential amplifier consists of:
a pair of amplifier transistors connected to a common current source and each connected to a supply voltage through a series load element; and
a pair of switches connected in parallel across said load elements and operable by said clock means for alternatingly bridging said load elements.

### Claim 5 (depends on 3)

The integrator of claim 3 wherein said differential amplifier consists of:
a pair of amplifier transistors connected to a common current source;
a load element connected in series through a first switching transistor with one of said amplifier transistors and connected in series through a second switching transistor with the other of said amplifier transistors;
a third switching transistor interconnected between the said one of said amplifier transistors and a supply voltage;
a fourth switching transistor interconnected between the other of said amplifier transistors and said supply voltage, said first and fourth switching transistors being simultaneously operated and said second and third switching transistors being simultaneously operated by said clock means.

### Claim 6 (depends on 1)

The integrator of claim 1 wherein said first and second polarity commutators each consist of a plurality of field effect transistor switches alternatingly operated by said clock means and each having a source-drain segment in a current path connecting the inputs of said polarity commutators to the outputs thereof.

### Claim 7 (depends on 1)

The integrator of claim 1 wherein said sampling stage has a sampling period and wherein a period between polarity reversals of said polarity commutator is equal to one or more sampling periods and wherein said polarity commutators are actuated during a switching state of said sampling stage during which said first capacitor storing a sampled signal is disconnected from the input of said first amplifier stage.