Threshold voltage tolerant logic

An integrated circuit logic gate formed on a semiconductor substrate, comprising:

• a first enhancement mode MESFET device having a threshold voltage deviation from a nominal threshold voltage value and having its source terminal connected to a first logical input and its drain and gate terminals connected to a first node;
• a first impedance connected between said first node and the first potential forming a current source;
• a second impedance connected between said first node and a second potential forming a current sink, the resultant voltage at said first node deviating from a nominal first voltage in response to said threshold voltage deviation of said first MESFET device;
• a second enhancement mode MESFET device formed in close proximity to said first MESFET device and having a threshold voltage deviation from said nominal threshold voltage substantially equal to said threshold voltage deviation of said first MESFET device and having its gate connected to said first node, its source connected to said second potential, and its drain connected to an output terminal for the circuit;
• a third impedance connected between said output terminal and said first potential for conducting current to said output node, the resultant voltage at said output node being substantially equal to a nominal output voltage in response to said deviation of said voltage at said first node compensating for the effect of said threshold voltage deviation of said second MESFET device;
• whereby a logical inverter function can be performed by the circuit.