# US 4,399,549 A · Odd number frequency division with symmetrical output

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- Number: US 4,399,549 A
- Document ID: US4399549A
- Status: Granted
- Kind: A
- Application number: 06/293,918
- Filed: 1981-08-18
- Granted: 1983-08-16
- Earliest claimed: 1981-08-18
- Assignees: Zenith Radio Corporation
- Inventors: Gopal K. Srivastava
- Web page: https://patentgrep.com/patent/US4399549A

## CPC

- H03K 23/58: Gating or clocking signals not applied to all stages, i.e. asynchronous counters (H03K23/74 - H03K23/84 take precedence)
- H03K 21/08: Output circuits
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A method and apparatus is described for dividing a clock frequency by any odd number to obtain a symmetrical output. Generally, some dividers in a chain of divide-by-two dividers are designated as controlled dividers and others are designated as uncontrolled dividers. The clock input of each controlled divider receives the output of an exclusive NOR gate, the inputs to which include the output of the last divider in the chain and either the clock signal or the output of a preceding divider, depending on certain criteria. The clock input of each uncontrolled divider receives the output of an immediately preceding divider. With this arrangement, the last divider in the chain develops a divided output which is symmetrical.

## Claims

### Claim 1

In a chain of dividers, each having a clock input and an output, a method of dividing a clock signal by an odd number N to obtain a symmetrical, divider output, comprising:
associating with each divider a binary digit one or zero so that the combination of the digits represents the number N in binary form;
selecting as controlled dividers the divider associated with the least significant digit and dividers associated with each binary zero digit;
selecting as uncontrolled dividers the divider associated with the most significant digit and the remaining dividers associated with each binary one digit;
exclusive NORing the output of the divider associated with the most significant digit with the clock signal to provide a first control signal;
applying the first control signal to the clock input of the divider associated with the least significant digit;
for every other controlled divider, exclusive NORing the output of the divider associated with the most significant digit with the output of an immediately preceding divider in the chain, and applying the resultant control signal to the clock input of the controlled divider; and
coupling to the clock input of each uncontrolled divider to the output of an immediately preceding divider,
whereby the divider associated with the most significant digit develops a symmetrical output whose frequency is N times lower than the frequency of the clock signal.

### Claim 2 (depends on 1)

A method as set forth in claim 1 wherein each divider is a divide-by-two divider.

### Claim 3

A chain of dividers for dividing a clock signal by an odd number N, comprising:
a plurality of dividers, each of which is associated with a binary digit one or zero so that the combination of the digits represents the number N in binary form;
a logic circuit for exclusive NORing the clock signal with the output of the divider associated with the most significant digit;
means for coupling the output of said logic circuit to the clock input of the divider associated with the least significant digit;
logic circuit means for applying to the clock input of each divider associated with a binary digit zero the exclusive NOR of the output of an immediately preceding divider and the output of the divider associated with the most significant digit; and
means for coupling, to the clock input of each remaining divider associated with a binary digit one, the output of an immediately preceding divider, whereby the divider associated with the most significant digit develops a symmetrical output whose frequency is N times lower than the frequency of the clock signal.

### Claim 4 (depends on 3)

A chain of dividers as set forth in claim 3 wherein each of the dividers is a divide-by-two divider.

### Claim 5 (depends on 4)

A chain of dividers as set forth in claim 4 wherein each of the dividers comprises a flip-flop.