# US 4,399,522 A · Non-volatile static RAM cell with enhanced conduction insulators

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- Number: US 4,399,522 A
- Document ID: US4399522A
- Status: Granted
- Kind: A
- Application number: 06/192,580
- Filed: 1980-09-30
- Granted: 1983-08-16
- Earliest claimed: 1980-09-30
- Assignees: International Business Machines Corporation
- Inventors: Harish N. Kotecha
- Web page: https://patentgrep.com/patent/US4399522A

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- H10D 30/682: {programmed by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction}
- Y10S 257/904: with passive components,, e.g. polysilicon resistors
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

This invention provides improved non-volatile semiconductor memories which include a volatile latch circuit having a data node and first and second cross-coupled transistors, at least one of the transistors has first and second control gates, a floating gate and an enhanced conduction insulator or dual electron injector structure disposed between the first control gate and the floating gate. The second control gate is connected to the storage node. A control voltage source is connected to the first control gate for transferring charge between the enhanced conduction insulator or dual electron injector structure and the data node.

## Claims

### Claim 1

A memory system comprising;
first and second cross-coupled transistors, one of said transistors having first and second control gates, a floating gate and a dual charge injector structure disposed between the first control gate and the floating gate,
first and second load elements coupled to said first and second transistors, respectively, forming at least one storage node,
said second control gate being coupled to said storage node, and
means for applying a control voltage to said first control gate.

### Claim 2

A memory system comprising;
first and second cross-coupled transistors each having a floating gate and first and second capacitors coupled to the floating gate, one of said capacitors including a dual electron injector structure,
first and second load elements coupled to said first and second transistors, respectively, forming first and second storage nodes,
said first storage node being coupled to said first capacitor of said first transistor and said second storage node being coupled to said first capacitor of said second transistor, and
means for applying a control voltage to said second capacitors.

### Claim 3

A memory system comprising;
first and second cross-coupled transistors, each transistor having first and second control gates, a floating gate and a dual electron injector structure disposed between the first control gate and the floating gate of each transistor,
first and second load elements coupled to said first and second transistors, respectively, forming first and second storage nodes,
the second control gate of said first transistor being coupled to said second storage node and the second control gate of said second transistor being coupled to said first storage node, and
means for applying a control voltage to said first control gates.

### Claim 4

A memory system comprising;
a volatile memory cell having a data node and first and second cross-coupled transistors, one of said transistors including:
a first capacitor,
a floating gate coupled to said data node through said first capacitor, and
a second capacitor coupled to said floating gate, said second capacitor including a dual charge injector structure, and
means coupled to said floating gate through said second capacitor for transferring charge between said floating gate and said charge injector structure.

### Claim 5 (depends on 4)

A memory system as set forth in claim 4 wherein said data node has alternate first and second charge conditions and said charge transfer means transfers charge between said floating gate and said charge injector structure only when said data node has said first condition.

### Claim 6 (depends on 5)

A memory system as set forth in claim 5 wherein said charge injector structure is an electron injector structure.

### Claim 7 (depends on 6)

A memory system as set forth in claim 6 wherein said first capacitor has a capacitance substantially larger than the capacitance of said second capacitor.

### Claim 8 (depends on 7)

A memory system as set forth in claim 7 wherein said electron injector structure is a dual electron injector structure having at least one layer of silicon-rich silicon dioxide.

### Claim 9 (depends on 8)

A memory system as set forth in claim 8 wherein said dual electron injector structure has two layers of silicon-rich silicon dioxide separated by a layer of substantially impurity-free silicon dioxide.

### Claim 10

A random access memory system comprising;
a semiconductor substrate,
a volatile memory cell having a data node formed in said substrate and first and second cross-coupled transistors, one of said transistors including:
a floating gate,
a first insulating layer disposed between said floating gate and said substrate,
a first control gate coupled to said data node,
a second insulating layer disposed between said floating gate and said first control gate,
a second control gate, and
a dual electron injector structure disposed between said floating gate and second control gate, and
means for applying control pulses to said second control gate for transferring data between said data node and said floating gate.

### Claim 11

A random access memory cell comprising;
a volatile memory cell having first and second cross-coupled field effect transistors and first and second data nodes, each of said transistors includes:
a first capacitor,
a floating gate connected to said first capacitor and
a second capacitor coupled to said floating, said second capacitor including a dual charge injector structure,
means for connecting said first capacitor of said first transistor to said second data node,
means for connecting said first capacitor of said second transistor to said first data node, and
means coupled through said second capacitor to said floating gate of each of said transistors for transferring charge between said floating gate and said charge injector structures.

### Claim 12 (depends on 11)

A random access memory cell as set forth in claim 11 wherein said volatile memory cell further includes first and second input/output transistors and first and second bit lines coupled to said first and second data nodes, respectively, through said first and second input/output transistors.