On board self-calibration of analog-to-digital and digital-to-analog converters
OwnerKhen-Sang Taninventor
Life of this patent
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Abstract
A method and apparatus is disclosed which corrects for errors produced in data acquisition systems. Disclosed is a method and circuit for correcting errors, such as mismatch between binary weighted capacitors and offset, in a charge redistribution, weighted capacitor array analog-to-digital converter. A self-calibrating, self-correcting circuit is comprised of a second binary array of capacitors which adds to the regular charge redistribution capacitor array an error correcting signal to compensate for the mismatch. This error correcting signal is then stored and the other error correcting signals for other capacitors in the regular capacitor array are determined and subsequently stored for later correction of other capacitance mismatch.
Claims11
A self calibrating charge-redistribution analog-to-digital converter comprising:
- a first binary weighted capacitor array having a plurality of capacitors, one plate of each of said capacitors being electrically connected to a node,
- a comparator having one input electrically connected to said node,
- first logic means connected to said comparator output and said array for selectively connecting said capacitors to preselected voltages, and
- at least one second binary weighted error capacitor array electrically connected to said node and having a plurality of capacitors for determining the error correcting signal required at said node to correct the binary mismatch of preselected capacitors in said first array, each said capacitors in said error capacitor array being connected through a scaling capacitor to said node.
A method of calibrating capacitors C.sub.1 -C.sub.N in an A/D-D/A having a binary weighted capacitor array C.sub.1 (LSB), C.sub.2, C.sub.3, C.sub.4 . . . C.sub.N (MSB) plus one additional capacitor C.sub.0 of weight corresponding to the least significant bit (LSB) in combination with an error correcting capacitor array combined at an analog summation node, comprising the steps of:
- (1) initializing the summation node to zero,
- (2) applying a first signal of one polarity and magnitude to C.sub.0 and a second signal of opposite polarity but same magnitude to C.sub.1 with the resulting signal E.sub.1 at the summing node being proportional to the error in capacitor C.sub.1,
- (3) converting signal E.sub.1 into a digital signal using said error correcting capacitor array,
- (4) initializing the summation node again to zero, a
- (5) applying a third signal of one polarity and magnitude to C.sub.0 and C.sub.1 and a fourth signal of opposite polarity but same magnitude to C.sub.2,
- (6) converting E.sub.1 into an analog signal using said error correcting capacitor array and applying said analog signal E.sub.1 to said summing node, with the resulting analog signal E.sub.2 at the summing node being proportional to the error in C.sub.2,
- (7) converting E.sub.2 into a digital signal using said error correcting capacitor array, and
- (8) repeating steps (4)-(7) for the remaining capacitors as required.
Dependencies are inferred from the claim text.