# US 4,399,412 A · Duty cycle monitor circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,399,412 A - Document ID: US4399412A - Status: Granted - Kind: A - Application number: 06/332,919 - Filed: 1981-12-21 - Granted: 1983-08-16 - Earliest claimed: 1981-12-21 - Assignees: GTE Automatic Electric Labs Inc. - Inventors: Gerald M. Rinaldi - Web page: https://patentgrep.com/patent/US4399412A ## CPC - H03K 5/1565: {the output pulses having a constant duty cycle} - H03K 5/19: Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) - H03K 5/26: the characteristic being duration, interval, position, frequency, or sequence - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A duty cycle monitor circuit which detects variations in the duty cycle of a monitored pulse by comparing its duty cycle with the pulse width of an external reference signal. A detection circuit detects the duty cycle variation of the monitored pulse after being periodically reset by the external reference signal. A storage circuit is clocked by the reference signal and operates to store the output signals of the detection circuit. Upon detection of a duty cycle failure the monitor can be cleared by external control or detection of a monitored pulse having a valid duty cycle. ## Claims ### Claim 1 A duty cycle monitor circuit for use in a switching system, including a source of reference signal pulses of first and second polarities and a clock signal source normally operated to provide clock signal pulses having a pulse width greater than the pulse width of said reference signal pulses, and abnormally operated to provide clock signal pulses having positive and negative going edges and a pulse width narrower than the pulse width of said reference signal pulses, said duty cycle monitor circuit comprising: detection means connected to said reference signal source and said clock signal source, operated in response to a reference signal pulse of said first polarity and contemporaneously occurring first and second edges of a clock signal pulse to provide a duty cycle detected signal; said detection means further operated in response to each reference signal pulse of said second polarity to clear said duty cycle detected signal; and storage means connected to said detection means and to said reference signal source, operated in response to said reference signal pulse of said second polarity and said duty cycle detected signal to provide a duty cycle failure signal. ### Claim 2 (depends on 1) A duty cycle monitor circuit as claimed in claim 1, wherein: said storage means is further operated in response to said reference signal pulse of said second polarity and an absence of said duty cycle detected signal to clear said duty cycle failure signal. ### Claim 3 (depends on 1) A duty cycle monitor circuit as claimed in claim 1, wherein there is further included: a clear signal source; said storage means further connected to said clear signal source, and further operated in response to said clear signal to clear said duty cycle failure signal. ### Claim 4 (depends on 1) A pulse monitor circuit as claimed in claim 1, wherein there is further included; a routining signal source, said pulse monitor circuit further comprising: gating means connected to said clock signal source and said routining signal source, operated in response to said routining signal to inhibit said clock signal from appearing at said detection means. ### Claim 5 (depends on 1) A duty cycle monitor circuit as claimed in claim 1, wherein said detection means comprise: a first flip-flop having a negative edge triggered clock input connected to said clock signal source and a clear input connected to said reference signal source operated to provide a rising edge detected signal; a second flip-flop having a positive edge triggered clock input connected to said clock signal source and a clear input connected to said reference signal source, operated to provide a falling edge detected signal; and gating means connected to said first and second flip-flops operated in response to said rising edge detected signal and said falling edge detected signal to provide said duty cycle detected signal. ### Claim 6 (depends on 5) A duty cycle monitor circuit as claimed in claim 5, wherein said storage means comprises: a flip-flop having a clock input connected to said reference signal source, a first data input connected to said gating means and a second data input connected to ground. ### Claim 7 (depends on 2) A duty cycle monitor circuit as claimed in claim 2, wherein said detection means comprise: a first flip-flop having a negative edge triggered clock input connected to said clock signal source and a clear input connected to said reference signal source operated to provide a rising edge detected signal; a second flip-flop having a positive edge triggered clock input connected to said clock signal source and a clear input connected to said reference signal source, operated to provide a falling edge detected signal; gating means connected to said first and second flip-flops operated in response to said rising edge detected signal and said falling edge detected signal to provide said duty cycle detected signal; and an inverter connected to said gating means, operated to provide an inverted duty cycle detected signal. ### Claim 8 (depends on 7) A pulse monitor circuit as claimed in claim 7, wherein said storage means comprises: a flip-flop having a clock input connected to said reference signal source, a first data input connected to said gating means, and a second data input connected to said inverter.