# US 4,399,411 A · Quantized video signal level interpolator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,399,411 A - Document ID: US4399411A - Status: Granted - Kind: A - Application number: 06/304,379 - Filed: 1981-09-22 - Granted: 1983-08-16 - Earliest claimed: 1981-09-22 - Assignees: RCA Corporation - Inventors: Donald F. Dion; Michael J. Cantella - Web page: https://patentgrep.com/patent/US4399411A ## CPC - G01R 13/26: Circuits for controlling the intensity of the electron beam {or the colour of the display} - G09G 1/002: {Intensity circuits (G09G1/06 - G09G1/28 take precedence)} - H03K 5/159: Applications of delay lines not covered by the preceding subgroups - H04N 5/14: Picture signal circuitry for video frequency region (cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A signal which changes from amplitude X to amplitude Z is applied to a resistor of value R which is series connected with an electrical L-C (inductor-capacitor) delay line unterminated at the opposite end and having a characteristic resistance of value R and one-way delay time T. An output terminal is coupled to the junction of the resistor and delay line. For a time duration 2 T after the input signal changes value, a signal of value (X+Z).div.2 appears at the output terminal and thereafter a signal of value Z appears. ## Claims ### Claim 1 A quantized signal level interpolator for interpolating at least one intermediate amplitude step into an input signal applied to an input terminal which signal changes from a first amplitude X to a second different amplitude Z, comprising in combination: a delay line of electrical length T with characteristic resistance value R and being unterminated at one end; a resistor series connected between said input terminal and other end of said delay line and being of value R; an output terminal coupled to said other end of said delay line, whereby when said input signal changes from amplitude X to amplitude Z a signal of amplitude intermediate X and Z appears at said output terminal until a time 2 T later when a signal of amplitude Z appears; and means responsive to the signals appearing at both ends of said delay line for producing a difference signal, corresponding to the sum of the signal at said other end and inverse of said signal at said one end and means having an output connected to said output terminal and responsive to said difference signal and signal at said one end for producing a signal which corresponds to the sum of those two signals. ### Claim 2 (depends on 1) The combination as set forth in claim 1, wherein said difference signal producing means comprises a differential amplifier producing a signal which is the difference of signals applied thereto from said delay line, and a potential divider having an intermediate tap and being connected between the output of said differential amplifier and circuit ground, said tap being connected to one input of said summing means. ### Claim 3 (depends on 1) The combination as set forth in claim 1 further comprising a second interpolator circuit similar to the first interpolator circuit and having its input terminal connected to said output terminal of said first circuit, the time delay of the delay line of the first circuit being equal to three times the delay time of the second delay line. ### Claim 4 (depends on 2) The combination as set forth in claim 2 further comprising a second interpolator circuit similar to the first interpolator circuit and having its input terminal connected to said output terminal of said first circuit, the time delay of the delay line of the first circuit being equal to three times the delay time of the second delay line. ### Claim 5 A quantized signal level interpolator for interpolating at least one intermediate amplitude step into an input signal applied to an input terminal, comprising in combination: means producing a digital signal which, from time to time, abruptly changes from one value to another, said means producing a signal which abruptly changes from a first amplitude X to a second different amplitude Z; a delay line of electrical length T with characteristic resistance value R and being unterminated at one end; impedance means series connected between said input terminal and other end of said delay line and having a resistive value R and having no reactive value; and an output terminal coupled to said other end of said delay line, said electrical length T being selected so that when said input signal changes from amplitude X to amplitude Z a signal of amplitude intermediate X and Z appears at said output terminal until a time 2 T later when a signal of amplitude Z appears. ### Claim 6 (depends on 5) The combination as set forth in claim 5 wherein said interpolator further comprises means responsive to the signals appearing at both ends of said delay line for producing a difference signal, corresponding to the sum of the signal at said other end and inverse of said signal at said one end and means having an output connected to said output terminal and responsive to said difference signal and signal at said one end for producing a signal which corresponds to the sum of those two signals. ### Claim 7 (depends on 6) The combination as set forth in claim 6 wherein said difference signal producing means comprises a differential amplifier producing a signal which is the difference of signals applied thereto from said delay line, and a potential divider having an intermediate tap and being connected between the output of said differential amplifier and circuit ground, said tap being connected to one input of said summing means. ### Claim 8 (depends on 6) The combination as set forth in claim 6 further comprising a second interpolator circuit similar to the first interpolator circuit and having its input terminal connected to said output terminal of said first circuit, the time delay of the delay line of the first circuit being equal to three times the delay time of the second delay line. ### Claim 9 (depends on 7) The combination as set forth in claim 7 further comprising a second interpolator circuit similar to the first interpolator circuit and having its input terminal connected to said output terminal of said first circuit, the time delay of the delay line of the first circuit being equal to three times the delay time of the second delay line.