# US 4,398,339 A · Fabrication method for high power MOS device

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- Number: US 4,398,339 A
- Document ID: US4398339A
- Status: Granted
- Kind: A
- Application number: 06/300,474
- Filed: 1981-09-09
- Granted: 1983-08-16
- Earliest claimed: 1977-04-15
- Assignees: Supertex, Inc.
- Inventors: Richard A. Blanchard; Benedict C. K. Choy
- Web page: https://patentgrep.com/patent/US4398339A

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V groov

## Claims

### Claim 1

In a method of fabricating a high power MOS semiconductor device comprising the steps of:
forming a substantially V-shaped groove in a semiconductor substrate through both a high conductivity region of one conductivity type and a region of opposite type conductivity that surrounds a substantial portion of said high conductivity region of one conductivity type,
forming a first insulating layer in said V-shaped groove,
forming a doped electrically conductive polysilicon gate electrode layer on the surface of said first insulating layer,
forming a second insulating layer on said polysilicon gate electrode layer,
forming an opening in said second insulating layer to expose a surface portion of said polysilicon gate electrode layer,
depositing electrical contacts to make separate source and drain connections to regions of said semiconductor substrate and to make electrical contact to said polysilicon gate electrode layer through said opening in said second insulating layer, one of said electrical contacts being located on said second insulating layer.

### Claim 2 (depends on 1)

The method of claim 1 wherein said source electrical contact being deposited over substantially the entire surface of said second and first insulating layers formed on one surface of said semiconductor substrate except for the surface portion containing the electrical contact to said polysilicon gate electrode layer, and said drain electrical contact being deposited in contact with a region of said semiconductor substrate along the opposite surface of said semiconductor substrate.

### Claim 3 (depends on 2)

The method of claim 2 wherein said source electrical contact being in electrical contact to both a portion of said high conductivity region of one conductivity type forming the source region and a region opposite type conductivity forming part of a channel region through an opening in said first insulating layer.

### Claim 4 (depends on 2)

The method of claim 2 including the steps of depositing said source electrical contact by first evaporating a thin layer of one metal followed by plating a thicker layer of another metal to provide a large heat sink.

### Claim 5

In a method of fabricating a high power MOS semiconductor device comprising the steps of:
forming a pair of spaced substantially V-shaped grooves in a semiconductor substrate through both a high conductivity region of one conductivity type and a region of opposite type conductivity that surrounds a substantial portion of said high conductivity region of one conductivity type,
forming a first insulating layer in said substantially V-shaped grooves,
forming a second insulating layer in said substantially V-shaped grooves,
forming a doped electrically conductive polysilicon gate electrode layer on the surface of said second insulating layer in each of said pair of substantially V-shaped grooves,
forming a third insulating layer on said polysilicon gate electrode layer,
forming an opening in said third insulating layer to expose a surface portion of said polysilicon gate electrode layer, and
depositing electrical contacts to make separate source and drain connections to regions of said semiconductor substrate and to make separate electrical contact to said polysilicon gate electrode layer through said opening in said third insulating layer, one of said electrical contacts being located on said third insulating layer.

### Claim 6 (depends on 5)

The method of claim 5 wherein the first insulating layer being silicon dioxide and said second insulating layer being silicon nitride.

### Claim 7 (depends on 5)

The method of claim 5 wherein one of said deposited electrical contacts contacting said semiconductor substrate between said pair of spaced V-shaped grooves.

### Claim 8 (depends on 5)

The method of claim 5, wherein said step of forming said third insulating layer on said polysilicon gate electrode layer comprising growing said insulating layer from said polysilicon gate electrode layer.

### Claim 9 (depends on 5)

The method of claim 5 further including the step of forming the deposited electrical contacts to provide a source contact over substantially all of said polysilicon gate electrode layer and in said grooves.

### Claim 10 (depends on 8)

The method of claim 8 further including the step of forming the deposited electrical contacts to provide a source contact over substantially all of said polysilicon gate electrode layer and in said grooves.