# US 4,398,301 A · Multiple preamplifiers with intervening overflow cell for charge coupled imaging devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,398,301 A - Document ID: US4398301A - Status: Granted - Kind: A - Application number: 06/186,108 - Filed: 1980-09-11 - Granted: 1983-08-09 - Earliest claimed: 1980-09-11 - Assignees: Fairchild Camera and Instrument Corporation - Inventors: Rudolph H. Dyck - Web page: https://patentgrep.com/patent/US4398301A ## CPC - H10F 39/153: {Two-dimensional or three-dimensional array CCD image sensors} - G11C 27/04: Shift registers - H04N 25/713: Transfer or readout registers; Split readout registers or multiple readout registers - H10D 44/454: {Output structures} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - G11C: STATIC STORES (semiconductor memory devices H10B) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Apparatus for amplifying output signals from a charge coupled area imaging device includes a resettable first floating gate amplifier connected to sense charge in the charge coupled device output register at a first location, a second floating gate amplifier connected to sense charge in the charge coupled device output register at a second location, and a charge limiting well disposed between the first location and the second location to remove charge in excess of a desired amount before the output signals are sensed at the second location. The dual preamplifiers permit optimization of the output signals from the charge coupled imaging device for two substantially different light levels by providing a substantially lower noise equivalent input signal level from the second preamplifier. ## Claims ### Claim 1 Apparatus for amplifying output signals comprising electrical charge in a serial output register in a charge coupled device, the apparatus comprising: first amplifier means for amplifying the output signals when they are supplied at a first location of the output register; at least one second amplifier means for amplifying the output signals when they are supplied to at least one location in the output register other than the first location; and signal limiting means disposed between the first location and at least one location other than the first location for limiting the output signals to a preselected amount after the output signals pass the first location. ### Claim 2 (depends on 1) Apparatus as in claim 1 wherein the signal limiting means removes charge in excess of a preselected amount. ### Claim 3 (depends on 2) Apparatus as in claim 2 wherein the signal limiting means includes a charge limiting well. ### Claim 4 (depends on 1) Apparatus as in claim 1 wherein the first amplifier means includes a first floating gate amplifier. ### Claim 5 (depends on 4) Apparatus as in claim 4 wherein the first floating gate amplifier is resettable. ### Claim 6 (depends on 4) Apparatus as in claim 4 wherein the at least one second amplifier means includes a second floating gate amplifier. ### Claim 7 (depends on 6) Apparatus as in claim 6 wherein the second floating gate amplifier includes a second sense node formed over the serial output register and is connected to a second field effect transistor. ### Claim 8 (depends on 7) Apparatus as in claim 7 further including a seventh and an eighth effect transistor wherein: the second sense node is connected to the gate of the second field effect transistor; the source of the second field effect transistor is connected to a third potential source and the drain of the second field effect transistor is connected to the gate and the source of the seventh field effect transistor and to the gate of the eighth field effect transistor; the source of the eighth field effect transistor is connected through a second resistance to ground and to a second output terminal for supplying output signals; and the drains of the seventh and eighth field transistors are connected to the second potential source. ### Claim 9 (depends on 7) Apparatus as in claim 7 wherein the second field effect transistor is a portion of a second inverter. ### Claim 10 (depends on 9) Apparatus as in claim 9 wherein the output of the second inverter is connected to second source follower means. ### Claim 11 (depends on 9) Apparatus as in claim 9 wherein the source potential of the second inverter circuit may be varied. ### Claim 12 (depends on 4) Apparatus as in claim 4 wherein the first floating gate amplifier includes a first sense node formed over the serial output register and is connected to a first field effect transistor. ### Claim 13 (depends on 12) Apparatus as in claim 12 further including a third, a fourth, and a fifth field effect transistor wherein: the first sense node is connected to the gate of the first field effect transistor; the source of the first field effect transistor is connected to a first potential supply; the drain of the first field effect transistor is connected to both the source and gate of the third field effect transistor and to the gate of the fourth field effect transistor; the source of the fourth field effect transistor is connected to the drain of the fifth field effect transistor and to the gate of the sixth field effect transistor; the gate and the source of the fifth field effect transistor are connected to ground potential; the source of the sixth field effect transistor is connected through a first resistance to ground and to a first terminal for supplying output signals; and the drains of the third, fourth and sixth field effect transistor are connected to a second potential source. ### Claim 14 (depends on 12) Apparatus as in claim 12 wherein the first field effect transistor is a portion of a first inverter circuit. ### Claim 15 (depends on 14) Apparatus as in claim 14 wherein the output of the first inverter is connected to first source follower means. ### Claim 16 (depends on 14) Apparatus as in claim 14 wherein the source potential of the first inverter circuit may be varied.