# US 4,398,268 A · Semiconductor integrated circuit device

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- Number: US 4,398,268 A
- Document ID: US4398268A
- Status: Granted
- Kind: A
- Application number: 06/171,274
- Filed: 1980-07-23
- Granted: 1983-08-09
- Earliest claimed: 1979-07-26
- Assignees: Fujitsu Limited
- Inventors: Kazuhiro Toyoda
- Web page: https://patentgrep.com/patent/US4398268A

## CPC

- G11C 11/416: Read-write [R-W] circuits
- G11C 11/4116: {with at least one cell access via separately connected emittors of said transistors or via multiple emittors, e.g. T2L, ECL}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An integrated injection logic (I.sup.2 L) memory where sink currents flowing into non-selected memory cells are supplied from clamp circuits, not from the selected memory cell. In addition, the potential of the selected bit line through which a write current flows is decreased by the clamp circuits.

## Claims

### Claim 1

A semiconductor integrated circuit device comprising:
a plurality of word lines;
a plurality of word drivers, each connected to one of said word lines;
a plurality of hold lines;
a plurality of pairs of bit lines, each bit line having a variable potential and each bit line pair selectively conducting an associated current including a sink current;
a plurality of bit drivers, each connected to a corresponding pair of said bit lines;
a plurality of memory cells of integrated injection logic, each connected to a corresponding one of said word lines, to a corresponding one of said hold lines and to a corresponding pair of said bit lines,
each memory cell including:
injectors comprising first and second transistors of a first conduction type which have a common emitter connected to said corresponding one of said word lines;
a flip-flop comprising cross-coupled third and fourth transistors of a second conduction type, connected to said first and second transistors respectively, and an emitter connected to the corresponding pair of said bit lines;
fifth and sixth transistors of a second conduction type, each comprising a base and a collector both connected in parallel with said third or fourth transistor, respectively and an emitter connected to the corresponding pair of said bit lines;
said third, fourth, fifth and sixth transistors being connected to the corresponding one of said hold lines; and
first clamp means for selectively raising the potential of a first bit line of each of said pairs of bit lines above that of the second bit line of each of said pairs of bit lines in response to a write enable signal and an input data signal, and for absorbing the sink current associated with each of said first bit lines.

### Claim 2 (depends on 1)

A device according to claim 1, further comprising second clamp means for raising the potentials of non-selected pairs of bit lines from that of a selected pair, and for absorbing the sink current associated with said non-selected pairs of bit lines, said selected pair being selected by said bit drivers.

### Claim 3 (depends on 1, 2)

A device according to claim 1 or 2, wherein said first clamp means comprises:
a plurality of pairs of first clamp transistors, each said pair being connected to a corresponding one of said pairs of bit lines; and
current switching means for selectively clamping the bases of said first clamp transistors in response to said write enable signal and said input data signal.

### Claim 4 (depends on 3)

A device according to claim 3, wherein said current switching means comprises:
a first current switch comprising seventh and eighth transistors controlled by said write enable signal and by a reference voltage, respectively;
a second current switch comprising ninth, tenth and eleventh transistors controlled by said reference voltage, by said write enable signal, and by said input data signal, respectively;
first and second current sources for supplying currents to said first and second current switches;
a first resistor connected to said seventh and ninth transistors; and
a second resistor connected to said tenth and eleventh transistors.

### Claim 5

A semiconductor integrated circuit device comprising:
a plurality of word lines;
a plurality of word drivers, each connected to one of said word lines;
a plurality of hold lines;
a plurality of pairs of bit lines, each bit line having a variable potential and each bit line pair selectively conducting an associated current including a sink current;
a plurality of bit drivers, each connected to a corresponding pair of said bit lines;
a plurality of memory cells of integrated injection logic, each connected to a corresponding one of said word lines, to a corresponding one of said hold lines and to a corresponding pair of said bit lines,
each memory cell including:
injectors comprising first and second transistors of a first conduction type which have a common emitter connected to said corresponding one of said word lines;
a flip-flop comprising cross-coupled third and fourth transistors of a second conduction type, connected to said first and second transistors respectively, and an emitter connected to the corresponding pair of said bit lines;
fifth and sixth transistors of a second conduction type, each comprising a base and a collector both connected in parallel with said third or fourth transistor, respectively, and an emitter connected to the corresponding pair of said bit lines;
said third, fourth, fifth and sixth transistors being connected to the corresponding one of said hold lines; and
clamp means for raising the potentials of non-selected pairs of said bit lines from that of a selected pair, and for absorbing the sink current associated with said non-selected pairs of bit lines, said selected pair being selected by said bit drivers.

### Claim 6 (depends on 2, 5)

A device according to claim 5 or 2, wherein said clamp means for raising the potentials of non-selected pairs of bit lines comprises:
a plurality of pairs of second clamp transistors, each connected to a corresponding one of said pairs of bit lines;
a plurality of resistors, each connected to the bases of one pair of said pairs of second clamp transistors;
a plurality of driving transistors, each connected to one of said resistors and to one of said bit drivers; and
a plurality of current sources, each supplying a current to one of said driving transistors.