# US 4,398,244 A · Interruptible microprogram sequencing unit and microprogrammed apparatus utilizing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,398,244 A - Document ID: US4398244A - Status: Granted - Kind: A - Application number: 06/147,100 - Filed: 1980-05-07 - Granted: 1983-08-09 - Earliest claimed: 1980-05-07 - Assignees: Fairchild Camera and Instrument Corporation - Inventors: Paul Chu; James B. Klingensmith - Web page: https://patentgrep.com/patent/US4398244A ## CPC - G06F 9/268: {Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An interruptible microprogram sequencing unit (MSU) for providing a sequence of microinstruction addresses to a control memory containing microinstructions for the operation of a microprogrammed apparatus. The MSU includes an address output for providing microinstruction addresses to the control memory, an address bus connected to the address output such that a plurality of microinstruction addresses applied to the address bus are sequentially provided to the address output, means connected to the address bus for applying the plurality of microinstruction addresses to the address bus, an interrupt return register operably connected to the address bus for receiving a microinstruction address from the address bus and storing the received microinstruction address, and means connected to the address bus for interrupting the sequence of microinstruction addresses and effecting storage of a microinstruction address on the address bus in the interrupt return register. ## Claims ### Claim 1 An interruptible microprogram sequencing unit for providing a sequence of microinstruction addresses to a control memory which contains a plurality of microinstructions for the operation of a microprogrammed apparatus, the microprogram sequencing unit comprising: (a) an address output for providing microinstruction addresses to the control memory, (b) an address bus connected to said address output such that a plurality of microinstruction addresses applied to said address bus are sequentially provided to said address output, (c) means connected to said address bus for applying said plurality of microinstruction addresses to said address bus, (d) an interrupt return register operably connected to said address bus for receiving a microtruction address from said address bus and storing said received microinstruction address, and (e) means connected to said address bus for interrupting said sequence of microinstruction addresses and effecting storage of a microinstruction address on said address bus in said interrupt return register. ### Claim 2 (depends on 1) An interruptible microprogram sequencing unit as defined by claim 1 and further including first address incrementing means including a microprogram counter and operably connected to said bus for incrementing addresses. ### Claim 3 (depends on 2) An interruptible microprogram sequencing unit as defined by claim 2 and further including second address incrementing means operably connected with said first address incrementing means and said bus for providing a skip address. ### Claim 4 (depends on 2) An interruptible microprogram sequencing unit as defined by claim 2 further including a multilevel storage means operably connected with said bus, said first address incrementing means, and said interrupt return register for storing a return address in response to multiple interrupts. ### Claim 5 (depends on 4) An interruptible microprogram sequencing unit as defined by claim 4 wherein said multilevel storage means includes status means for indicating overflow and underflow conditions. ### Claim 6 (depends on 4) An interruptible microprogram sequencing unit as defined by claim 4 wherein said means for applying externally supplied addresses to said bus includes an interrupt register for storing externally supplied addresses and operably connected to provide a stored address to said bus. ### Claim 7 (depends on 6) An interruptible microprogram sequencing unit as defined by claim 6 and further including means for receiving an interrupt address from said interrupt register and directly from an external address source. ### Claim 8 (depends on 7) An interruptible microprogram sequencing unit as defined by claim 7 and further including means for inhibiting an interrupt. ### Claim 9 (depends on 6) An interruptible microprogram sequencing unit as defined by claim 6 and further including means for connecting said interrupt register directly to said address output. ### Claim 10 (depends on 6) An interruptible microprogram sequencing unit as defined by claim 6 and further including register/counter means connected to said address bus for storing an address or for storing a decrementible count, said register/counter means including means for indicating a zero count. ### Claim 11 (depends on 10) An interruptible microprogram sequencing unit as defined by claim 10 and including means for loading a start address in said first address incrementing means and for loading a count in said register/counter means whereby a sequence of microinstructions are addressed. ### Claim 12 (depends on 11) An interruptible microprogram sequencing unit as defined by claim 11 and further including multiplexer means for selectively connecting said means for supplying externally supplied addresses, said interrupt register, and said register/counter means to said bus. ### Claim 13 (depends on 12) An interruptible microprogram sequencing unit as defined by claim 12 and further including means for connecting said multiplexer means to said multilevel storage means for storing addresses from said multiplexer means and means for connecting said multilevel storage means to said interrupt register and said register/counter means for restoring addresses. ### Claim 14 (depends on 13) An interruptible microprogram sequencing unit as defined by claim 13 and further including means for connecting said multilevel storage means to said means for applying externally supplied addresses whereby contents of said multilevel storage means can be transferred to external storage means. ### Claim 15 (depends on 1, 13) An interruptible microprogram sequencing unit as defined by claims 1 or 13 and further including a repeat address register operably connected to said bus for storing an address on said bus and for supplying an address to said bus. ### Claim 16 (depends on 15) An interruptible microprogram sequencing unit as defined by claim 15 and further including multiway input means and multiplexer means responsive to source control field inputs for applying an address with offset to said bus. ### Claim 17 (depends on 16) An interruptible microprogram sequencing unit as defined by claim 16 wherein said bus comprises 16 bit lines whereby said unit can address 64K (K=1024) locations of memory. ### Claim 18 (depends on 16) An interruptible microprogram sequencing unit as defined by claim 16 and further including test input means connected to said address bus for providing microprogram test instruction addresses to said address bus, said test input means including enable, polarity control, and test condition inputs. ### Claim 19 A microprogrammed apparatus comprising a plurality of data paths for manipulating data, a control memory connected to said data paths for sequentially providing a plurality of addressable microinstructions contained in said memory to said data paths for controlling said data paths, and a microprogram sequencing unit connected to said control memory for providing a sequence of microinstruction addresses to said control memory, said microinstruction sequencing unit including an address output for providing addressing microinstruction addresses to said control memory, an address bus connected to said address output such that a plurality of microinstruction addresses applied to said address bus are sequentially provided to said address output, means connected to said address bus for applying said plurality of microinstruction addresses to said address bus, an interrupt return register operably connected to said address bus for receiving a microinstruction address from said address bus and storing said received microinstruction address, and means connected to said address bus for interrupting said sequence of microinstruction addresses and effecting storage of a microinstruction address on said address bus in said interrupt return register. ### Claim 20 (depends on 19) A microprogrammed apparatus as defined by claim 19 wherein said microprogram sequencing unit further includes a first address incrementing means including a microprogram counter and operably connected to said bus for incrementing addresses. ### Claim 21 (depends on 20) A microprogrammed apparatus as defined by claim 20 wherein said microprogram sequencing unit further includes a second address incrementing means operably connected with said first address incrementing means and said bus for providing a skip address. ### Claim 22 (depends on 20) A microprogrammed apparatus as defined by claim 20 wherein said microprogram sequencing unit further includes a multilevel storage means operably connected with said bus, said first address incrementing means, and said interrupt return register for storing a return address in response to multiple interrupts. ### Claim 23 (depends on 22) A microprogrammed apparatus as defined by claim 22 wherein said microprogram sequencing unit further includes status means connected to said address bus for indicating overflow and underflow conditions in said multilevel storage means. ### Claim 24 (depends on 22) A microprogrammed apparatus as defined by claim 22 wherein said microprogram sequencing unit further includes an interrupt register for storing externally supplied addresses and operably connected to provide a stored address to said bus. ### Claim 25 (depends on 24) A microprogrammed apparatus as defined by claim 24 wherein said microprogram sequencing unit further includes means for receiving an interrupt address from said interrupt register and directly from an external address source. ### Claim 26 (depends on 25) A microprogrammed apparatus as defined by claim 25 wherein said microprogram sequencing unit further includes means for inhibiting an interrupt. ### Claim 27 (depends on 25) A microprogrammed apparatus as defined by claim 25 wherein said microprogram sequencing unit further includes means for connecting said interrupt register directly to said address output. ### Claim 28 (depends on 25) A microprogrammed apparatus as defined by claim 25 wherein said microprogram sequencing unit further includes register/counter means connected to said address bus for storing an address and for storing a decrementible count, said register/counter means including means for indicating a zero count. ### Claim 29 (depends on 28) A microprogrammed apparatus as defined by claim 28 wherein said microprogram sequencing unit further includes means for loading a start address in said first address incrementing means and for loading a count in said register/counter means whereby a sequence of microinstructions are addressed. ### Claim 30 (depends on 29) A microprogrammed apparatus as defined by claim 29 wherein said microprogram sequencing unit further includes multiplexer means for selectively connecting said means for supplying externally supplied addresses, said interrupt register, and said register/counter means to said bus. ### Claim 31 (depends on 30) A microprogrammed apparatus as defined by claim 30 wherein said microprogram sequencing unit further includes means for connecting said multiplexer means to said multilevel storage means for storing addresses from said multiplexer means and means for connecting said multilevel storage means to said interrupt register and said register/counter means for restoring addresses. ### Claim 32 (depends on 31) A microprogrammed apparatus as defined by claim 31 wherein said microprogram sequencing unit further includes means for connecting said multilevel storage means to said means for applying externally supplied addresses whereby contents of said multilevel storage means can be transferred to external storage means. ### Claim 33 (depends on 19, 32) A microprogrammed apparatus as defined by claims 19 or 32 wherein said microprogram sequencing unit further includes a repeat address register operably connected to said bus for storing an address on said bus and for supplying an address to said bus. ### Claim 34 (depends on 33) A microprogrammed apparatus as defined by claim 33 wherein said microprogram sequencing unit further includes multiway input means and multiplexer means responsive to source control field inputs for applying an address with offset to said bus. ### Claim 35 (depends on 34) A microprogrammed apparatus as defined by claim 34 wherein said microprogram sequencing unit further includes 16 bit lines whereby said unit can address 64K locations of memory. ### Claim 36 (depends on 34) A microprogrammed apparatus as defined by claim 34 wherein said microprogram sequencing unit further includes test input means connected to said address bus for providing microprogram test instruction addresses to said address bus, said test input means including enable, polarity control, and test condition inputs.