# US 4,398,243 A · Data processing system having a unique instruction processor system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 4,398,243 A - Document ID: US4398243A - Status: Granted - Kind: A - Application number: 06/143,651 - Filed: 1980-04-25 - Granted: 1983-08-09 - Earliest claimed: 1980-04-25 - Assignees: Data General Corporation - Inventors: Kenneth D. Holberger; James E. Veres; Michael L. Ziegler; Carl Henry - Web page: https://patentgrep.com/patent/US4398243A ## CPC - G06F 9/342: {Extension of operand address space} - G06F 9/26: Address formation of the next micro-instruction (G06F9/28 takes precedence){; Microprogram storage or retrieval arrangements} - G06F 9/30: Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) - G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's - G06F 11/14: Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16) - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches - G06F 12/1009: using page tables, e.g. page table structures - G06F 12/14: Protection against unauthorised use of memory {or access to memory} - G06F 11/106: {Correcting systematically all correctable errors, i.e. scrubbing} - G06F 12/0623: {for memory modules} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different level of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit. ## Claims ### Claim 1 In a data processing system, an instruction processor means for decoding a plurality of first instructions forming a first designated basic instruction set the addresses of which have a first selected number of bits and a plurality of second instructions forming a second designated extended instruction set the addresses of which have a second selected number of bits different from said first selected number, each of said first or second instructions including at least an operating code portion which includes a selected bit code combination which identifies whether said instruction is from said basic instruction set or from said extended instruction set and some of said first and second instructions further including at least one displacement portion, said instruction processor means comprising instruction decode register means having at least two register regions, a first of said regions designated to temporarily store said operating code portion of an instruction and said at least one other region designated to temporarily store a displacement portion; means for supplying an incoming instruction of said basic instruction set or said extended instruction set; instruction decode shifter means connected to said instruction supplying means and responsive to said incoming instruction for entering said incoming instruction into said instruction decode register means so that said first designated region temporarily stores the operating code portion thereof and said at least one other designated region, if required, temporarily stores a displacement portion thereof; means responsive to the selected bit code combination of each incoming instruction for identifying whether said instruction is from basic instruction set or from said extended instruction set; and means for decoding the operating code portion of said identified instruction supplied thereto from said instruction decode register means to produce a plurality of operating code descriptors associated with said decoded instruction and for producing a starting address of one or more microinstructions associated with said decoded instruction. ### Claim 2 (depends on 1) In a data processing system in accordance with claim 1 wherein said instruction processor means further includes displacement handling means connected to said instruction decode register means and to said decoding means and responsive to a displacement portion of an instruction, if included therein, from said instruction decode register means and to selected ones of said operating code descriptors from said decoding means for providing a displacement word having a predetermied number of bits, the displacement portions of which are arranged in a selected format for use by said data processing system. ### Claim 3 (depends on 2) In a data processing system in accordance with claim 2 wherein said displacement handling means includes sign extend logic means responsive to selected ones of said operating code descriptors and to a displacement portion of an instruction, if included therein, for extending the displacement portion by sign extended data, if necessary, to produce said displacement word. ### Claim 4 (depends on 2) In a data processing system in accordance with claim 2 wherein said displacement handling means includes zero extend logic means responsive to selected ones of said operating code descriptors and to a displacement portion of an instruction, if included therein, for extending the displacement portion by a selected number of zero bits, if necessary, to produce said displacement word. ### Claim 5 (depends on 2) In a data processing system in accordance with claim 2 wherein said displacement handling means further includes means responsive to said displacement word for supplying said displacement word to said system for use in an arithmetic or logical operation. ### Claim 6 (depends on 2) In a data processing system in accordance with claim 2 wherein said displacement handling means further includes means responsive to said displacement word for supplying a logical address word to provide a memory reference address to said system. ### Claim 7 (depends on 2) In a data processing system in accordance with claim 2 wherein said instruction processor means decodes said incoming instruction to provide said starting address and said displacement word, if required, while the one or more microinstructions associated with the starting address of the preceding decoded instruction are being executed. ### Claim 8 (depends on 1) In a data processing system in accordance with claim 1 said instruction processor means further including instruction cache storage means for storing a plurality of instructions only; means for identifying whether a requested instruction is stored in said instruction cache storage means; said instruction cache storage means being responsive to the address of said requested instruction stored therein when said identifying means indicates that said requested instruction is stored in said instruction cache storage means for supplying said requested instruction to said instruction decode shifter means. ### Claim 9 (depends on 8) In a data processing system in accordance with claim 8 wherein said data processing system includes a main memory means, said instruction processor means further including means for accessing said requested instruction from said main memory storage means when said identifying means indicates that said requested instruction is not stored in said instruction cache storage means. ### Claim 10 (depends on 9) In a data processing system in accordance with claim 9, said instruction processor means further including means for providing a direct transmission path to said instruction decode shifter means for a requested instruction which has been accessed from said main memory storage means. ### Claim 11 (depends on 1) In a data processing system in accordance with claim 1 wherein said instruction decoding means is an array of programmable read-only-memories connected to said instruction decode register means and responsive to the operating code portions of an instruction supplied from said first region thereof for decoding said operating code portion to produce the starting microaddress of one or more microinstructions associated with said decoded instruction. ### Claim 12 (depends on 11) A data processing system in accordance with claim 11 wherein said array of programmable read-only-memories includes first programmable read-only-memory means for decoding instructions of said basic instruction set and second programmable read-only-memory means for decoding instructions of said extended instruction set. ### Claim 13 (depends on 12) A data processing system in accordance with claim 12 said instruction processor means further including means responsive to said selected bit code combination for enabling a selected one of said first or second programmable read-only-memory means to decode said instruction depending on whether the instruction to be decoded is from said basic instruction set or from said extended instruction set. ### Claim 14 (depends on 13) A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 1 in bit .0. and 1001 in bits 12-15 of said instruction for identifying a first group of instructions from said extended instruction set. ### Claim 15 (depends on 13) A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 1 in bit .0. and 011000 in bits 10-15 of said instruction for identifying a first group of instructions from said extended instruction set. ### Claim 16 (depends on 13) A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 1 in bit .0., a 0 in bit 5 and 111000 in bits 10-15 of said instruction for identifying a third group of instructions from said extended instruction set. ### Claim 17 (depends on 13) A data processing system in accordance with claim 13 wherein said selected bit code combination comprises a 0 in bit .0. and 1000 in bits 12-15 of said instruction for identifying instructions from said basic instruction set.